pca9539 datasheet

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Table Of Contents

DB, DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

INT

RESET

P00

P01

P02

P03

P04

P05

P06

P07

GND

SDA

SCL

P17

P16

P15

P14

P13

P12

P11

P10

24 23 22 21 20

7 8 9 10 11

RGE PACKAGE

(TOP VIEW)

INT

P10

P11 SDA

P06

P07

GND

SCL

P12

P00

P01

P02

P03

P04

P05

P17

P16

P15

P14

P13

RESET

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

PCA9539

SCPS130G –AUGUST 2005–REVISED JUNE 2014

PCA9539 Remote 16-Bit I

C and SMBus Low-Power I/O Expander With Interrupt Output,

Reset, and Configuration Registers

1 Features 2 Description

This 16-bit I/O expander for the two-line bidirectional

• Low Standby-Current Consumption of 1 μA Max

bus (I

C) is designed for 2.3-V to 5.5-V V

• I

C to Parallel Port Expander

operation. It provides general-purpose remote I/O

• Open-Drain Active-Low Interrupt Output

expansion for most microcontroller families via the I

interface [serial clock (SCL), serial data (SDA)].

• Active-Low Reset Input

• 5-V Tolerant I/O Ports

The PCA9539 consists of two 8-bit Configuration

(input or output selection), Input Port, Output Port,

• Compatible With Most Microcontrollers

and Polarity Inversion (active-high or active-low

• 400-kHz Fast I

C Bus

operation) registers. At power-on, the I/Os are

• Polarity Inversion Register

configured as inputs. The system master can enable

the I/Os as either inputs or outputs by writing to the

• Address by Two Hardware Address Pins for Use

I/O configuration bits. The data for each input or

of up to Four Devices

output is kept in the corresponding Input or output

• Latched Outputs With High-Current Drive

Capability for Directly Driving LEDs

inverted with the Polarity Inversion register. All

• Latch-Up Performance Exceeds 100 mA Per

registers can be read by the system master.

JESD 78, Class II

Device Information

(1)

• ESD Protection Exceeds JESD 22

PART NUMBER PACKAGE BODY SIZE (NOM)

– 2000-V Human-Body Model (A114-A)

SSOP (24) 8.20 mm × 5.30 mm

– 1000-V Charged-Device Model (C101)

TVSOP (24) 5.00 mm × 4.40 mm

PCA9539 SOIC (24) 15.40 mm × 7.50 mm

TSSOP (24) 7.80 mm × 4.40 mm

VQFN (24) 4.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Summary of content (43 pages)

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Sample & Buy Product Folder Support & Community Tools & Software Technical Documents PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 PCA9539 Remote 16-Bit I2C and SMBus Low-Power I/O Expander With Interrupt Output, Reset, and Configuration Registers 1 Features • • • • • • • • • 1 • • • 2 Description Low Standby-Current Consumption of 1 μA Max I2C to Parallel Port Expander Open-Drain Active-Low Interrupt Output Active-Low Reset Input 5-V Tolerant I/O Ports Compatible With Most Microcontrollers 40
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Description ............................................................. Revision History..................................................... Description (Continued) ........................................ Pin Configuration and Functions ......................... Specifications.........................................................
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 4 Description (Continued) The system master can reset the PCA9539 in the event of a time-out or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without de-powering the part.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com Pin Functions PIN NO. SOIC (DW), SSOP (DB), QSOP (DBQ), TSSOP (PW), AND TVSOP (DGV) QFN (RGE) INT 1 22 Interrupt output. Connect to VCC through a pullup resistor. A1 2 23 Address input. Connect directly to VCC or ground. RESET 3 24 Active-low reset input. Connect to VCC through a pullup resistor if no active connection is used. P00 4 1 P-port input/output. Push-pull design structure. P01 5 2 P-port input/output.
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 6 UNIT V (2) –0.5 6 V –0.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com 6.4 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input diode clamp voltage II = –18 mA VPOR Power-on reset voltage VI = VCC or GND, IO = 0 IOH = –8 mA P-port high-level output voltage (2) VOH IOH = –10 mA VCC MIN 2.3 V to 5.5 V –1.2 VPOR 2.3 V 1.8 3V 2.6 4.75 V 4.1 2.3 V 1.7 3V 2.5 4.
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 I2C Interface Timing Requirements 6.5 over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13) MIN MAX UNIT 0 400 kHz 2 fscl I C clock frequency tsch I2C clock high time 0.6 tscl I2C clock low time 1.3 tsp I2C spike time I C serial-data setup time tsdh I2C serial-data hold time ticr I2C input rise time μs 50 2 tsds μs 100 ns 0 2 ns ns 20 + 0.1Cb (1) 300 ns 20 + 0.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com 6.8 Typical Characteristics TA = 25°C (unless otherwise noted) 55 30 SCL = V CC 50 V CC = 5 V 25 ICC – Supply Current – nA ICC – Supply Current – µA 45 40 f SCL = 400 kHz I/Os Unloaded 35 30 25 V CC = 3.3 V 20 15 10 20 V CC = 5 V 15 V CC = 3.3 V 10 0 -50 -25 0 25 50 75 0 -50 100 TA – Free-Air Tem perature – °C -25 0 25 50 75 100 TA – Free-Air Tem perature – °C Figure 1. Supply Current vs Temperature Figure 2.
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 Typical Characteristics (continued) TA = 25°C (unless otherwise noted) 300 35 V CC = 2.5 V, ISINK = 10 m A 275 V CC = 2.5 V ISOURCE – I/O Source Current – mA V OL – Output Low Voltage – mV 250 225 200 175 V CC = 5 V, ISINK = 10 m A 150 125 100 75 V CC = 2.5 V, ISINK = 1 m A 50 30 TA = –40°C 25 TA = 25°C 20 15 10 TA = 125°C 5 V CC = 5 V, ISINK = 1 m A 25 0 0.0 0 -50 -25 0 25 50 75 0.1 0.2 100 0.3 0.4 0.5 0.6 0.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com 7 Parameter Measurement Information VCC RL = 1 kΩ SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Three Bytes for Complete Device Programming Stop Condition (P) Start Address Address Condition Bit 7 Bit 6 (S) (MSB) Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) Stop Condition (P) tsch 0.7 × VCC SCL 0.3 × VCC ticr ticf tbuf tsts tPHL tPLH tsp 0.7 × VCC SDA 0.
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 Parameter Measurement Information (continued) VCC RL = 4.7 kΩ INT DUT CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION ACK From Slave Start Condition 8 Bits (One Data Byte) From Port R/W Slave Address S 1 1 1 0 1 1 2 3 4 5 A1 A0 1 6 7 8 Data 1 A ACK From Slave Data From Port A Data 2 1 P A A tir tir B B INT A tiv tsps A Data Into Port Address Data 1 0.7 × VCC INT 0.3 × VCC SCL Data 2 0.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com Parameter Measurement Information (continued) 500 W Pn 2 × VCC DUT CL = 50 pF (see Note A) 500 W P-PORT LOAD CONFIGURATION 0.7 × VCC SCL P0 A P3 0.3 × VCC Slave ACK ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ SDA Pn tpv (see Note B) Unstable Data Last Stable Bit WRITE MODE (R/W = 0) 0.7 × VCC SCL P0 A tps P3 0.3 × VCC tph 0.7 × VCC Pn 0.3 × VCC READ MODE (R/W = 1) A. CL includes probe and jig capacitance. B. tpv is measured from 0.
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 Parameter Measurement Information (continued) VCC Pn RL = 1 kΩ DUT 500 W 2 × VCC DUT SDA CL = 50 pF (see Note A) 500 W CL = 50 pF (see Note A) P-PORT LOAD CONFIGURATION SDA LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 y VCC tRESET RESET VCC/2 tREC tw Pn VCC/2 tRESET A. CL includes probe and jig capacitance. B.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com 8 Detailed Description 8.1 Functional Block Diagram INT A0 A1 SCL SDA PCA9539 1 Interrupt Logic LP Filter 21 2 P07−P00 22 23 I2C Bus Control Input Filter Shift Register 16 Bits I/O Port P17−P10 Write Pulse 3 RESET VCC GND 24 12 Power-On Reset Read Pulse A. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages. B. All I/Os are set to inputs at reset. Figure 17.
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PCA9539 www.ti.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com 8.2 Device Functional Modes 8.2.1 RESET Input A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PCA9539 registers and I2C/SMBus state machine are held in their default states until RESET is once again high. This input requires a pullup resistor to VCC, if no active connection is used. 8.2.1.1 RESET Errata If RESET voltage set higher than VCC, current will flow from RESET pin to VCC pin.
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 Device Functional Modes (continued) 8.2.4.1 Interrupt Errata The INT will be improperly de-asserted if the following two conditions occur: 1. The last I2C command byte (register pointer) written to the device was 00h. NOTE This generally means the last operation with the device was a Read of the input register. However, the command byte may have been written with 00h without ever going on to read the input register.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com Programming (continued) SDA SCL S P Start Condition Stop Condition Figure 19. Definition Of Start And Stop Conditions SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 20. Bit Transfer Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 21. Acknowledgment On I2C Bus 8.3.2 Register Map Table 1.
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 8.3.2.1 Device Address Figure 22 shows the address byte of the PCA9539. R/W Slave Address 1 1 1 0 Fixed 1 A1 A0 Programmable Figure 22. Pca9539 Address Table 2.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com 8.3.2.3 Register Descriptions The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level.
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 The eight registers within the PCA9539 are configured to operate as four register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversion ports, and Configuration ports. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 24 and Figure 25). For example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 Slave Address S 1 1 1 0 1 www.ti.com Acknowledge From Slave A1 A0 0 Slave Address Acknowledge From Slave A A Command Byte S R/W 1 1 1 0 1 Data From Lower or Upper Byte of Register Acknowledge From Slave A1 A0 1 A MSB LSB Data A First Byte R/W At this moment, master transmitter becomes master receiver, and slave receiver becomes slave transmitter.
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PCA9539 www.ti.com 1 SCL SCPS130G – AUGUST 2005 – REVISED JUNE 2014 2 3 4 5 6 7 8 9 I0.x SDA S 1 1 1 0 1 A1 A0 1 R/W A 00 Acknowledge From Slave I1.x A 10 I0.x A I1.x 03 A Acknowledge From Master Acknowledge From Master P No Acknowledge From Master tps tph 1 12 Acknowledge From Master Read From Port 0 Data Into Port 0 Data 00 Data 01 Data 02 Data 03 tph tps Read From Port 1 Data 10 Data Into Port 1 Data 11 Data 12 INT tiv tir A.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com 9 Application And Implementation 9.1 Typical Application Figure 29 shows an application in which the PCA9539 can be used. Subsystem 1 (e.g., Temperature Sensor) INT VCC (5 V) 10 kW VCC 10 kW 10 kW 24 10 kW 22 SCL Master Controller SDA 23 SCL SDA Subsystem 2 (e.g.
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 Typical Application (continued) 9.1.1 Detailed Design Procedure 9.1.1.1 Minimizing ICC When I/O Is Used To Control Led When an I/O is used to control an LED, normally it is connected to VCC through a resistor (see Figure 29). Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com 10 Power Supply Recommendations 10.1 Power-On Reset Requirements In the event of a glitch or data corruption, PCA9539 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 32 and Figure 33.
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PCA9539 www.ti.com SCPS130G – AUGUST 2005 – REVISED JUNE 2014 Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 34 and Table 8 provide more information on how to measure these specifications. VCC VCC_GH Time VCC_GW Figure 34.
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PCA9539 SCPS130G – AUGUST 2005 – REVISED JUNE 2014 www.ti.com 11 Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 — TI Glossary.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 10-Dec-2020 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-Dec-2020 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCA9539DBQR Package Package Pins Type Drawing SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PCA9539DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 PCA9539DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-Dec-2020 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9539DBQR SSOP DBQ 24 2500 853.0 449.0 35.0 PCA9539DBR SSOP DB 24 2000 853.0 449.0 35.0 PCA9539DGVR TVSOP DGV 24 2000 853.0 449.0 35.0 PCA9539DWR SOIC DW 24 2000 350.0 350.0 43.0 PCA9539PWR TSSOP PW 24 2000 853.0 449.0 35.0 PCA9539RGER VQFN RGE 24 3000 853.0 449.0 35.
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PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.15 7.9 7.7 NOTE 3 12 13 B 0.30 0.19 0.1 C A B 24X 4.5 4.3 NOTE 4 1.2 MAX 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0 -8 0.75 0.50 DETAIL A A 20 TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2.
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EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE SYMM 24X (1.5) (R0.05) TYP 1 24 24X (0.45) 22X (0.65) SYMM 13 12 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) 0.05 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 15.000 4220208/A 02/2017 NOTES: (continued) 6.
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EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24 24X (0.45) 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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GENERIC PACKAGE VIEW RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details.
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PACKAGE OUTLINE VQFN - 1 mm max height RGE0024C PLASTIC QUAD FLATPACK- NO LEAD A 4.1 3.9 B 4.1 3.9 PIN 1 INDEX AREA 1 MAX C SEATING PLANE 0.05 0.00 0.08 C 2X 2.5 2.1±0.1 (0.2) TYP 12 7 20X 0.5 6 13 25 2X 2.5 SYMM 1 PIN 1 ID (OPTIONAL) 18 24X 0.30 0.18 24 19 SYMM 24X 0.50 0.30 0.1 0.05 C A B C 4224376 / A 07/2018 NOTES: 1. 2. 3. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
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EXAMPLE BOARD LAYOUT VQFN - 1 mm max height RGE0024C PLASTIC QUAD FLATPACK- NO LEAD (3.8) ( 2.1) 19 24 24X (0.6) 24X (0.24) 1 18 20X (0.5) 25 SYMM (3.8) 2X (0.8) (Ø0.2) VIA TYP 6 13 (R0.05) 12 7 2X(0.8) SYMM LAND PATTERN EXAMPLE SCALE: 20X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4224376 / A 07/2018 NOTES: (continued) 4. 5.
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EXAMPLE STENCIL DESIGN VQFN - 1 mm max height RGE0024C PLASTIC QUAD FLATPACK- NO LEAD (0.19) 4X ( 0.94) 19 24 24X (0.58) 24X (0.24) 1 18 20X (0.5) SYMM (3.8) (0.57) TYP 6 13 (R0.05) TYP METAL TYP 25 7 SYMM 12 (0.57) TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80% PRINTED COVERAGE BY AREA SCALE: 20X 4224376 / A 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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