Features • Number of Keys: • • • • • • • • • • • • • • • • • • • • • – Comms Mode: 1 to 12 keys (1 to 9 if wheel or slider option enabled) – Standalone Mode: 1 to 5 keys Technology: – Patented spread-spectrum QTouchADC charge-transfer Number of Output Lines: – Comms Mode: Up to 10 channels can be configured as outputs (but they will replace the keys) – Standalone Mode: 1 to 5 channels can be configured as outputs Key Outline Sizes: – 5 mm x 5 mm or larger (panel thickness dependent) Key Spacings: – 6 mm
1. Pinouts and Schematics 1.1 1.1.1 Pinouts 20-pin SOIC/TSSOP – Comms Mode KEY8/GPO6 1 20 KEY9/GPO7 KEY7/GPO5 2 19 KEY10/GPO8 KEY6/GPO4 3 18 KEY11/GPO9 KEY5/GPO3 4 17 CHANGE KEY4/GPO2 5 16 SCL KEY3/GPO1 6 15 N/C KEY2/GPO0 7 14 RESET KEY1 8 13 SDA KEY0 9 12 MODE 10 11 VDD OUT3 1 20 OUT4 OUT2 2 19 OUT5 KEY6 3 18 OUT6 KEY5 4 17 N/C KEY4 5 16 N/C KEY3 6 15 PXOUT KEY2 7 14 RESET GUARD 8 13 N/C PROX 9 12 MODE 10 11 VDD VSS 1.1.
AT42QT2120 KEY7/GPO5 KEY8/GPO6 KEY9/GPO7 KEY10/GPO8 KEY11/GPO9 20 19 18 17 16 KEY6/GPO4 1 15 CHANGE KEY5/GPO3 2 14 SCL KEY4/GPO2 3 13 N/C KEY3/GPO1 4 12 RESET KEY2/GPO0 5 11 SDA KEY6 1 15 N/C KEY5 2 14 N/C KEY4 3 13 PXOUT KEY3 4 12 RESET KEY2 5 11 N/C 6 7 8 9 10 KEY1 KEY0 VSS VDD MODE OUT2 OUT3 OUT4 OUT5 OUT6 20 19 18 17 16 QT2120 20-pin VQFN – Standalone Mode 7 8 9 10 PROX VSS VDD MODE QT2120 6 1.1.
1.2 Pin Descriptions 1.2.1 20-pin SOIC/TSSOP Table 1-1. Pin Listings (20-pin SOIC/TSSOP) Name (Comms) Name (Standalone) Type 1 KEY8/ GPO6 OUT3 2 KEY7/ GPO5 3 Pin Description If Unused...
AT42QT2120 1.2.2 20-pin VQFN Table 1-2. Pin Listings (20-pin VQFN) Name (Comms) Name (Standalone) Type 1 KEY6/ GPO4 KEY6 2 KEY5/ GPO3 3 Pin Description If Unused...
1.3 Schematics Figure 1-1. 20-pin SOIC/TSSOP – Comms Mode VDD VDD 11 R12 VDD 14 V DD RESET R13 15 R15 N/C 17 13 16 CHANGE SDA SCL CHANGE SDA SCL 12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 18 19 20 1 2 3 4 5 6 7 8 9 KEY 11 KEY 10 KEY 9 KEY 8 KEY 7 KEY 6 KEY 5 KEY 4 KEY 3 KEY 2 KEY 1 KEY 0 May be used for wheel or slider 10 MODE V SS R14 KEY11/GPO9 KEY10/GPO8 KEY9/GPO7 KEY8/GPO6 KEY7GPO5 KEY6/GPO4 KEY5/GPO3 KEY4/GPO2 KEY3/GPO1 KEY2/GPO0 KEY1 KEY0 VSS VSS Figure 1-2.
AT42QT2120 Figure 1-3. 20-pin VQFN – Comms Mode VDD VDD 9 R12 12 VD D VDD RESET KEY11/GPO9 KEY10/GPO8 KEY9/GPO7 KEY8/GPO6 KEY7/GPO5 KEY6/GPO4 KEY5/GPO3 KEY4/GPO2 KEY3/GPO1 KEY2/GPO0 KEY1 KEY0 R13 R15 CHANGE SDA SCL 13 N/C 15 11 14 CHANGE SDA SCL 10 V SS R14 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 KEY 11 KEY 10 KEY 9 KEY 8 KEY 7 KEY 6 KEY 5 KEY 4 KEY 3 KEY 2 KEY 1 May be used for wheel or slider KEY 0 8 MODE 16 17 18 19 20 1 2 3 4 5 6 7 VSS VSS Figure 1-4.
2. Overview 2.1 Introduction The AT42QT2120 (QT2120) is a QTouchADC sensor driver. The device can sense from one to 12 keys, dependent on mode. Three of the keys can be used as sense channels for a slider or wheel, leaving a maximum of nine standard touch keys. The device also supports the use of proximity sensors and a guard channel. The QT2120 includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions, and the outputs are fully debounced.
AT42QT2120 2.3 Keys Dependent on mode, the QT2120 can have a minimum of one key and a maximum of 12 keys. These can be constructed in different shapes and sizes. See “Features” on page 1 for the recommended dimensions. The possible combinations of keys are: Comms mode: • 1 to 12 keys or • 1 to 9 keys plus 1 slider/wheel • Key channels 2 to 11 can be reassigned as general outputs, if required Note: Any number of keys can be configured as proximity channels.
2.6 Adjacent Key Suppression (AKS) Technology The device includes the Atmel patented Adjacent Key Suppression (AKS) technology, to allow the use of tightly spaced keys on a keypad with no loss of selectability by the user. There can be up to three AKS groups, implemented so that only one key in the group may be reported as being touched at any one time. Once a key in a particular AKS group is in detect no other key in that group can go into detect.
AT42QT2120 2.9 Calibration Writing a nonzero value to the calibration byte can force a recalibration at any time. This can be useful to clear out a stuck key condition after a prolonged period of uninterrupted detection. A calibration command executes 15 burst cycles at LPM 1 and sets the CALIBRATE bit of the Detection Status register during the calibration sequence. Note: 2.10 A calibration command should be sent whenever Key Control bit 0 (EN) is changed.
In standalone mode the detect threshold is set to a fixed value of 10 counts of change with respect to the internal reference level for the guard channel and 10 counts for the other six keys (including proximity channel). The reference level has the ability to adjust itself slowly in accordance with the drift compensation mechanism. The drift mechanism will drift toward touch at a rate of 160 ms x 20 = 3.2 seconds (Towards Touch Drift (TTD) register) and away from touch at a rate of 160 ms x 5 = 0.
AT42QT2120 2.11.6 Drift Hold Time Drift Hold Time (DHT) is used to restrict drift on all keys while one or more keys are activated. DHT restricts the drifting on all keys until approximately four seconds after all touches have been removed. This feature is particularly useful in cases of high-density keypads where touching a key or hovering a finger over the keypad would cause untouched keys to drift, and therefore create a sensitivity shift, and ultimately inhibit touch detection.
3.3 PCB Cleanliness Modern no-clean flux is generally compatible with capacitive sensing circuits. ! CAUTION: If a PCB is reworked to correct soldering faults relating to the device, or to any associated traces or components, be sure that you fully understand the nature of the flux used during the rework process. Leakage currents from hygroscopic ionic residues can stop capacitive sensors from functioning. If you have any doubts, a thorough cleaning after rework may be the only safe option.
AT42QT2120 4. I2C-compatible Communications (Comms Mode Only) 4.1 4.1.1 I2C-compatible Protocol Protocol The I2C-compatible protocol is based around access to an address table (see Table 5-1 on page 18) and supports multibyte reads and writes. The maximum clock rate is 400 kHz. See Section A on page 41 for an overview of I2C bus operation. 4.1.
1. The host initiates the transfer by sending the START condition 2. The host follows this by sending the slave address of the device together with the WRITE bit. 3. The device sends an ACK. 4. The host then sends the memory address within the device it wishes to write to. 5. The device sends an ACK. 6. The host transmits one or more data bytes; each is acknowledged by the device (unless trying to write to an invalid address). Valid write address are 5 – 51. 7.
AT42QT2120 Note: 4.4 Reading the 16-bit reference and signal values is not an automatic operation; reading the first byte of a 16-bit value does not lock the other byte. As a result glitches in the reported value may be seen as values increase from 255 to 256, or decrease from 256 to 255. This device also supports the use of a repeated START condition as an alternative to the Stop condition. SDA, SCL The I2C-compatible bus transmits data and clock with SDA and SCL respectively.
5. Setups 5.1 Introduction The device calibrates and processes signals using a number of algorithms specifically designed to provide for high survivability in the face of adverse environmental challenges. User-defined Setups are employed to alter these algorithms to suit each application. These Setups are loaded into the device over the I2C-compatible serial interfaces. In standalone mode these settings are fixed to predetermined values. Table 5-1.
AT42QT2120 Table 5-1.
Table 5-1.
AT42QT2120 5.5 Addresses 3 – 4: Key Status Table 5-5. Key Status Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3 KEY7 KEY6 KEY5 KEY4 KEY3 KEY2 KEY1 KEY0 KEY11 KEY10 KEY9 KEY8 4 Reserved KEY0 – KEY11: These bits indicate which keys are in detection, if any. Touched keys report as 1, untouched or disabled keys report as 0. A change in these bytes will cause the CHANGE line to trigger. 5.6 Address 5: Slider Position Table 5-6.
5.9 Address 8: Low Power (LP) Mode Table 5-9. Address Bit 7 Bit 6 LP Mode Bit 5 Bit 4 8 Bit 3 Bit 2 Bit 1 Bit 0 LP MODE LP MODE: This 8-bit value determines the number of 16 ms intervals between key measurements. Longer intervals between measurements yield a lower power consumption but at the expense of a slower response to touch. Setting Time 0 Power Down 1 16 ms 2 32 ms 3 48 ms 4 64 ms ...254 4.064 s 255 4.
AT42QT2120 Figure 5-1. Thresholds and Away From Touch Drift Signal Threshold Hysteresis Reference Output The device drift compensates using a slew-rate limited change to the reference level; the threshold and hysteresis values are slaved to this reference. When a finger is sensed, the signal increases due to capacitance being added to Cx. An isolated, untouched foreign object (a coin, or a water film) will cause the signal to drop very slightly due to an enhancement of coupling.
5.11 Address 11: Detection Integrator (DI) Table 5-11. Address Bit 7 Bit 6 Bit 5 Detection Integrator Bit 4 11 Bit 3 Bit 2 Bit 1 Bit 0 DI DI: Allows the DI level to be set for each key. This 8-bit value controls the number of consecutive measurements that must be confirmed as having passed the key threshold before that key is registered as being in detect. The minimum value for the DI filter is 1. A settings of 0 for the DI also defaults to 1. Default: 4 (maximum = 32) 5.
AT42QT2120 This feature is particularly useful in cases of high-density keypads where touching a key or hovering a finger over the keypad would cause untouched keys to drift, and therefore create a sensitivity shift, and ultimately inhibit any touch detection. It is expressed in 0.16 s increments. DHT default value: 25 DHT range: 0 – 255 5.14 Address 14: Slider Options Table 5-14.
5.15 Address 15: Charge Time Table 5-15. Address Bit 7 Bit 6 Bit 5 15 Charge Time Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 CHARGE TIME Prolongs the charge-transfer period of signal acquisition by 1 µs per count. Allows full charge-transfer for keys with heavy Rs / Cx loading. Range: 0 – 255 Default: 0 5.16 Address 16 – 27: Detect Threshold (DTHR) Table 5-16.
AT42QT2120 GPO: If set to 0, this key is a driven-low output. If set to 1 then the output is driven high. Setting this bit only has an effect if the EN bit is set to 1. EN: If set to 0, indicates that this key is to be used as a touch channel. Setting this bit to 1 will disable the key for touch use and make the channel pin an output. Note: It is not possible to enable Channel 0 or Channel 1 as an output. Setting the GPO bit on these channels will only have the effect of disabling the key.
Table 5-19. Sample n Oversample for “n” Bits Scaling n Bits Gained (n) 4 2 n 1 1 0 (Pulse = 0x0 / Scale = 0x00) 4 2 1 (Pulse = 0x2 / Scale = 0x01) 16 4 2 (Pulse = 0x4 / Scale = 0x02) 64 8 3 (Pulse = 0x6 / Scale = 0x03) 256 16 4 (Pulse = 0x8 / Scale = 0x04) 1024 32 5 (Pulse = 0x0A / Scale = 0x05) 4096 64 6 (Pulse = 0x0C / Scale = 0x06) 16384 128 7 (Pulse = 0x0E / Scale = 0x07) Consideration should be taken on the overall effect on timing when setting Pulse values.
AT42QT2120 5.19 Address 52 – 75: Key Signal Table 5-20. Address Bit 7 Bit 6 Bit 5 Key Signal Bit 4 Bit 3 Bit 2 52 MSByte OF KEY SIGNAL FOR KEY 0 53 LSByte OF KEY SIGNAL FOR KEY 0 : : 74 MSByte OF KEY SIGNAL FOR KEY 11 75 LSByte OF KEY SIGNAL FOR KEY 11 Bit 1 Bit 0 KEY SIGNAL: addresses 52 – 75 allow key signals to be read for each key, starting with key 0. There are two bytes of data for each key.
6. Specifications 6.1 Absolute Maximum Specifications Vdd –0.5 to +6 V Max continuous pin current, any control or drive pin ±10 mA Short circuit duration to ground, any pin infinite Short circuit duration to Vdd, any pin infinite Voltage forced onto any pin –0.5 V to (Vdd + 0.5) V CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to the device.
AT42QT2120 6.4 Timing Specifications Parameter Description Minimum Typical Maximum Units Notes DI setting × 16 ms – LP mode + (DI setting × 16 ms) ms Under host control 10.5 12.5 – kHz Modulated spread-spectrum (chirp) Can be longer if burst is very long. TR Response time FQT Sample frequency TD Power-up delay to operate/calibration time – <230 – ms FI2C I2C-compatible clock rate – – 400 kHz – Fm Burst modulation, percentage 15 – % – – – µs 2 µs at 1.
6.5 Power Consumption 6.5.1 1 Channel Enabled Table 6-1. Power Consumption (µA) LP Mode 5V 4.2 V 3.6 V 3.3 V 3V 2.5 V 2V 1.8 V 0 <1 <1 <1 <1 <1 <1 <1 <1 1 910 720 590 530 475 385 310 280 2 790 625 515 465 420 340 280 255 3 750 595 490 445 400 330 265 245 4 730 580 480 430 390 320 260 240 5 720 570 460 415 385 315 255 235 255 670 535 445 405 360 300 245 225 Pulse = 0 and Scale = 0 Figure 6-1.
AT42QT2120 6.5.2 12 Channels Enabled 255 Table 6-2. Power Consumption (µA) LP Mode 5V 4.2 V 3.6 V 3.3 V 3V 2.5 V 2V 1.8 V 0 <1 <1 <1 <1 <1 <1 <1 <1 1 1095 860 700 630 560 460 370 330 2 880 700 575 515 460 380 305 280 3 810 645 530 480 425 350 285 260 4 780 615 510 455 410 340 275 250 5 760 600 490 440 400 330 270 240 255 675 535 445 410 360 295 245 225 Pulse = 0 and Scale = 0 Figure 6-2.
6.6 6.6.
AT42QT2120 6.6.2 AT42QT2120-XU – 20-pin TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AC INDEX MARK PIN 1 4.50 (0.177) 6.50 (0.256) 4.30 (0.169) 6.25 (0.246) 6.60 (.260) 6.40 (.252) 0.65 (.0256) BSC 0.30 (0.012) 0.19 (0.007) 1.20 (0.047) MAX 0.15 (0.006) 0.05 (0.002) SEATING PLANE 0.20 (0.008) 0.09 (0.004) 0º ~ 8º 0.75 (0.030) 0.45 (0.018) 10/23/03 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 20X, (Formerly 20T), 20-lead, 4.
6.6.3 AT42QT2120-MMH – 20-pin VQFN D C y Pin 1 ID E SIDE VIEW TOP VIEW A1 A D2 16 17 18 19 20 COMMON DIMENSIONS (Unit of Measure = mm) C0.18 (8X) 15 Pin #1 Chamfer (C 0.3) 14 2 e E2 13 MIN NOM MAX A 0.75 0.80 0.85 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 SYMBOL 1 3 C 12 4 11 5 b 10 9 8 7 6 K L BOTTOM VIEW 0.3 Ref (4x) NOTE 0.152 D 2.90 3.00 3.10 D2 1.40 1.55 1.70 E 2.90 3.00 3.10 E2 1.40 1.55 1.70 e – 0.45 – L 0.35 0.40 0.45 K 0.
AT42QT2120 6.7 6.7.1 Marking AT42QT2120X-SU Shortened part number Date Code Pin 1 QT2120 2R0 Code Revision 2.0 Released Date Code Description W=Week code W week code number 1-52 where: A=1 B=2 .... Z=26 then using the underscore A=27...
6.7.2 AT42QT2120X-XU Shortened part number 2120 Pin 1 2R0 Date Code Code Revision 2.0 Released Date Code Description W=Week code W week code number 1-52 where: A=1 B=2 .... Z=26 then using the underscore A=27...
AT42QT2120 6.7.3 AT42QT2120X-MMH Pin 1 Identification Code Revision 2.0 Prereleased (NOTE POSITION - Released) Shortened part number in hexadecimal “848” = “2120” 848 20 Date Code (NOTE POSITION - Released) Date Code Description W=Week code W week code number 1-52 where: A=1 B=2 .... Z=26 then using the underscore A=27...
6.8 Part Number Part Number Order Code Description AT42QT2120-SU AT42QT2120-SUR QS589 20-pin 0.300 inch wide body, SOIC RoHS-compliant IC AT42QT2120-XU AT42QT2120-XUR QS589 20-pin 4.4 mm body, TSSOP RoHS-compliant IC AT42QT2120-MMH AT42QT2120-MMHR QS589 20-pad 3 × 3 × 0.
AT42QT2120 Appendix A. A.1 I2C-compatible Operation Interface Bus The device communicates with the host over an I 2 C bus. The following sections give an overview of the bus; more detailed information is available from www.i2C-bus.org. Devices are connected to the I2C bus as shown in Figure A-1. Both bus lines are connected to Vdd via pullup resistors. The bus drivers of all I2C devices must be open-drain type.
A.3 START and STOP Conditions The host initiates and terminates a data transmission. The transmission is initiated when the host issues a START condition on the bus, and is terminated when the host issues a STOP condition. Between the START and STOP conditions, the bus is considered busy. As shown in Figure A-3, START and STOP conditions are signaled by changing the level of the SDA line when the SCL line is high. Figure A-3. START and STOP Conditions SDA SCL START A.
AT42QT2120 Figure A-5. Data Byte Format Data MSB Data LSB ACK 8 9 Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 Data Byte SLA+R/W A.6 7 Stop or Next Data Byte Combining Address and Data Bytes into a Transmission A transmission consists of a START condition, an SLA+R/W, one or more data bytes and a STOP condition. The wired “ANDing” of the SCL line is used to implement handshaking between the host and the device.
Associated Documents • QTAN0079 – Buttons, Sliders and Wheels Touch Sensors Design Guide • QTAN0087 – Proximity Design Guide • Atmel AVR3000: QTouch Conducted Immunity Application Note Revision History 44 Revision Number History Revision A – November 2011 Initial release of document for code revision 1.5 Revision B – December 2011 Release of document for code revision 1.7 (rev 1.6 unreleased) Revision C – February 2012 Small amendment to diagram (code revision 1.
AT42QT2120 Notes 45 9634E–AT42–06/12
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