Integration Guide

SMK900 Integration Guide Revision 4
#define GetExecType() $uf1(0x00)
#define GetRSSI() $uf1(0x01)
#define TransferConfigRAMBUF() $uf1(0x08)
#define TransferConfigRAM() $uf1(0x09)
#define TransferConfigEEPROM() $uf1(0x0A)
#define ResetFactoryDefaults() $uf1(0x0B)
#define Send(count) $uf1(0x20, count)
#define Delay(delay) $uf1(0x24, delay)
#define SetPinMirror(type) $uf1(0x28, type)
#define I2CPowerBus_Activate() $uf2(0x00)
#define I2CPowerBus_Deactivate() $uf2(0x01)
#define I2C_Stop() $uf2(0x04)
#define I2C_ReadAck() $uf2(0x05)
#define I2C_ReadNak() $uf2(0x06)
#define I2C_Start(addr_rw) $uf2(0x20, addr_rw)
#define I2C_Write(val) $uf2(0x21, val)
#define GetPinIn(pinID) $uf3(pinID)
#define GetPinDir(pinID) $uf3(pinID+0x10)
#define SetPinOut(pinID, val) $uf3(pinID, val)
#define SetPinDir(pinID, dir) $uf3(pinID+0x10, dir)
#define GetPerReg(reg) $uf4(reg)
#define SetPerReg(reg, val) $uf4(reg, val)
#define GetSignatureRow(memOffset) $uf5(memOffset)
//here are the IO mapping to real XMEGA pins. Note that XMEGA PA1 reserved for I2CPowerBus, Mesh PA2/PA3 are
//reserved for I2C. PA5 is reserved to CTS. All those are potentially system critical,
//so access is NOT granted to them.
//-IO PIN---+---XMEGA PIN --+----EQV OEM DNT NAME---+---------- DNT-MESH Special function name
// | | |
// 0 | PA0 | ADC_EXT_RC | ADC_EXT
// 1 | PA4 | GPIO3 |
// 2 | PA6 | RTS | RTS
// 3 | PA7 | ADC0 | ADC0
// 4 | PB0 | ADC1 | ADC1
// 5 | PB2 | DAC0 | DAC0
// 6 | PB3 | DAC1 | DAC1
// 7 | PC4 | SS |
(SPI_SS), OC1A (TIMER TCC1 wave out ch A)
// 8 | PC5 | MOSI | SPI_MOSI, OC1B
(TIMER TCC1 wave out ch B)
// 9 | PC6 | MISO | SPI_MISO
// 10 | PC7 | SCLK | SPI_SCLK, MIRROR
PIN
// 11 | PD2 | DCD | DCD
(Broadcast phase indicator)
// 12 | PD3 | ACT | ACT (TX
LED, this is non critical, thus can be changed)
#define _PA0 0
#define _PA4 1
#define _PA6 2
#define _PA7 3
#define _PB0 4
#define _PB2 5
#define _PB3 6
#define _PC4 7
#define _PC5 8
#define _PC6 9
#define _PC7 10
#define _PD2 11
#define _PD3 12
//PERIPHERIAL REGISTER TABLE
#define _EVSYS_CH0MUX 0x0000
#define _EVSYS_CH1MUX 0x0100
#define _EVSYS_CH0CTRL 0x0001
#define _EVSYS_CH1CTRL 0x0101
#define _PORTA_PIN0CTRL 0x0002
#define _PORTA_PIN4CTRL 0x0003
#define _PORTA_PIN6CTRL 0x0004
#define _PORTA_PIN7CTRL 0x0104
#define _PORTB_PIN0CTRL 0x0005
#define _PORTB_PIN2CTRL 0x0006
#define _PORTB_PIN3CTRL 0x0106
#define _PORTC_PIN4CTRL 0x0007
#define _PORTC_PIN5CTRL 0x0107
#define _PORTC_PIN6CTRL 0x0207
#define _PORTC_PIN7CTRL 0x0307
#define _PORTD_PIN2CTRL 0x0008
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