COM20020 COM20020 ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM FEATURES • • • • • • • • • • • • • • 24-Pin Embedded Network Controller/ Transceiver/RAM Ideal for Industrial/Factory Automation and Automotive Applications Deterministic, 2.5 Mbps, Token Passing ARCNET Protocol Minimal Microcontroller and Media Interface Logic Required Flexible Microcontroller Interface for Use with 80XX, 68XX, etc.
TABLE OF CONTENTS FEATURES ........................................................................................................................................1 GENERAL DESCRIPTION .................................................................................................................1 PIN CONFIGURATION.......................................................................................................................3 DESCRIPTION OF PIN FUNCTIONS .............................................
network. The deterministic nature of ARCNET is essential in mission critical applications. The integration of the 2Kx8 RAM buffer on-chip, the Command Chaining feature, the 2.5 Mbps maximum data rate, and the internal diagnostics make the COM20020 the highest performance industrial communications device available. With only one COM20020 and one microcontroller, a complete communications node may be implemented. controller optimized for use in industrial and automotive applications.
DESCRIPTION OF PIN FUNCTIONS DIP PIN NO. PLCC PIN NO. NAME SYMBOL DESCRIPTION MICROCONTROLLER INTERFACE 1-3 1-3 Address 0-2 A0/nMUX, A1,A2/ALE Input. On a non-multiplexed bus, these signals are directly connected to the low bits of the host address bus. On a multiplexed address/data bus, A0/nMUX is tied low, A1 is left open, and A2 is tied to the Address Latch Enable signal of the host. A1 is connected to an internal pull-up resistor. 4-11 4-6,8-12 Data 0-7 AD0-AD2, D3-D7 Input/Output.
DIP PIN NO. PLCC PIN NO. NAME SYMBOL DESCRIPTION 19 23 nReset in nRESET IN Input. This active low signal issued by the microcontroller executes a hardware reset. It is used to activate the internal reset circuitry within the COM20020. 20 24 nInterrupt nINTR Output. This active low signal is generated by the COM20020 when an enabled interrupt condition occurs. nINTR returns to its inactive state when the interrupt status condition or the corresponding interrupt mask bit is reset.
DIP PIN NO. PLCC PIN NO. NAME SYMBOL DESCRIPTION instead, it must be connected to XTAL1 with a 390Ω pull-up resistor, and XTAL2 should be left floating. 24 15,28 Power Supply VDD +5 Volt Power Supply pin. 12 7,14,22 Ground VSS Ground pin.
Power On Reconfigure Timer has Timed Out Send Reconfigure Burst Read Node ID Write ID to RAM Buffer 1 Set NID=ID Y Start Reconfiguration Timer (840 mS) N N Invitation to Transmit to this ID? Y Y TA? Transmit NAK Y Y Y RI? N Y ACK? Y N No Activity for 74.
PROTOCOL DESCRIPTION following protocol description assumes a 2.5 Mbps data rate. For slower data rates, an internal clock divider scales down the clock frequency. Thus all timeout values are scaled up as shown in the following table: NETWORK PROTOCOL Communication on the network is based on a token passing protocol. Establishment of the network configuration and management of the network protocol are handled entirely by the COM20020's internal microcoded sequencer.
When any COM20020 senses an idle line for greater than 82µS, which occurs only when the token is lost, each COM20020 starts an internal timeout equal to 146µs times the quantity 255 minus its own ID. The COM20020 starts network reconfiguration by sending an invitation to transmit first to itself and then to all other nodes by decrementing the destination Node ID.
Unlike asynchronous protocols, there is a constant amount of time separating each data byte. On a 2.5 Mbps network, each byte takes exactly 11 clock intervals of 400ns each. As a result, one byte is transmitted every 4.4µS and the time to transmit a message can be precisely determined. The line idles in a spacing (logic "0") condition. A logic "0" is defined as no line activity and a logic "1" is defined as a negative pulse of 200nS duration.
• A single COUNT character which is the 2's complement of the number of data bytes to follow if a short packet is sent, or 00H followed by a COUNT character if a long packet is sent • N data bytes where COUNT = 256-N (or 512N for a long packet) • Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X16 + X15 + X2 + 1. Data Packets A Data Packet consists of the actual data being sent to another node.
SYSTEM DESCRIPTION will not be changed until hardware Refer to Description of Pin MICROCONTROLLER INTERFACE The top halves of Figures 2 and 3 illustrate typical COM20020 interfaces to the microcontrollers. The interfaces consist of an 8bit data bus, an address bus, and a control bus. In order to support a wide range of microcontrollers without requiring glue logic and without increasing the number of pins, the COM20020 automatically detects and adapts to the type of microcontroller being used.
XTAL1 COM20020 XTAL2 AD0-AD7 ALE A15 RESET AD0-AD2, D3-D7 A2/BALE RXIN nCS nRESET IN nTXEN 75176B or Equiv. nPULSE1 nRD nRD/nDS nWR nINT1 nWR/DIR nINTR nPULSE2 GND Differential Driver Configuration A0/nMUX XTAL1 8051 * Media Interface may be replaced with Figure A, B or C.
XTAL1 COM20020 XTAL2 D0-D7 A0 D0-D7 A0/nMUX RXIN A1 A1 A2 A2/BALE A7 nCS nRES nRESET IN nIOS nRD/nDS R/nW nIRQ1 nWR/nDIR nINTR nPULSE1 nPULSE2 GND Differential Driver Configuration XTAL1 6801 75176B or Equiv. TXEN 27 pF * Media Interface may be replaced with Figure A, B or C. XTAL2 27 pF 20MHz XTAL FIGURE 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE +5V HYC9068 or HYC9088 10 uF RXIN RXIN + 0.
TRANSMISSION MEDIA INTERFACE reception of data consisting of 1, 1, 0. The bottom halves of Figures 2 and 3 illustrate the COM20020 interface to the transmission media used to connect the node to the network. Table 1 lists different types of cable which are suitable for ARCNET applications.
RT RT +VCC +VCC RBIAS RBIAS 75176B or Equiv. COM20020 +VCC COM20020 RBIAS COM20020 FIGURE 4 - COM20020 NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS ONLY) 1 1 20MHZ CLOCK (FOR REF.
The Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid Configuration. Like the Backplane Configuration, the Differential Driver Configuration does not isolate the node from the media. In typical applications, the serial backplane is terminated at both ends and a bias is provided by the external pull-up resistor. The RXIN signal is directly connected to the cable via an internal Schmitt trigger. A negative pulse on this input indicates a logic "1".
A0/nMUX A1 A2/BALE ADDRESS DECODING CIRCUITRY 2K x 8 RAM ADDITIONAL REGISTERS AD0-AD2, D3-D7 nINTR nRESET IN STATUS/ COMMAND REGISTER RESET LOGIC MICROSEQUENCER AND WORKING REGISTERS TX/RX LOGIC OSCILLATOR nRD/nDS nWR/DIR nCS BUS ARBITRATION CIRCUITRY RECONFIGURATION TIMER NODE ID LOGIC FIGURE 6 - INTERNAL BLOCK DIAGRAM 18 nPULSE1 nPULSE2 nTXEN RXIN XTAL1 XTAL2
Table 1 - Typical Media NOMINAL IMPEDANCE ATTENUATION PER 1000 FT. AT 5MHZ RG-62 Belden #86262 93Ω 5.5dB RG-59/U Belden #89108 75Ω 7.0dB RG-11/U Belden #89108 75Ω 5.5dB IBM Type 1* Belden #89688 150Ω 7.0dB IBM Type 3* Telephone Twisted Pair Belden #1155A 100Ω 17.9dB COMCODE 26 AWG Twisted Pair Part #105-064-703 105Ω 16.0dB CABLE TYPE *Non-plenum-rated cables of this type are also available.
Table 2 - Read Register Summary READ REGISTER STATUS MSB RI X X POR TEST RECON TMA LSB ADDRESS TA 00 X 01 DIAG.
Table 3 - Write Register Summary WRITE LSB REGISTER NEW NEXTID TA INTERRUPT MASK D2 D1 D0 COMMAND 0 A10 A9 A8 ADDRESS PTR HIGH A4 A3 A2 A1 A0 ADDRESS PTR LOW D5 D4 D3 D2 D1 D0 DATA 0 0 0 0 0 0 RESERVED TXEN ET1 ET2 BACKPLANE SUBAD1 SUBAD0 CONFIGURATION ADDRESS MSB 00 RI 0 0 0 01 D7 D6 D5 D4 D3 02 RDDATA AUTOINC 0 0 03 A7 A6 A5 04 D7 D6 05 0 0 06 RESET CCHEN EXCNAK RECON TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 TENTID NID7 NID6
INTERNAL REGISTERS loaded with the contents of COM20020 Internal Memory upon writing Address Pointer low only once. The COM20020 contains eight internal registers. Tables 2 and 3 illustrate the COM20020 register map. Reserved locations should not be accessed. All undefined bits are read as undefined and must be written as logic "0".
Transmitter is disabled, the Receiver portion of the device is still functional and will provide the user with useful information about the network. The Node ID Register defaults to the value 0000 0000 upon hardware reset only. Chaining operation. The Status Register defaults to the value 1XX1 0001 upon either hardware or software reset. Next ID Register The Diagnostic Status Register contains seven read-only bits which help the user troubleshoot the network or node operation.
Configuration Register Setup Register The Configuration Register is a read/write register which is used to configure the different modes of the COM20020. The Configuration Register defaults to the value 0001 1000 upon hardware reset only. SUBAD0 and SUBAD1 point to selection in Register 7. The Setup Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (see the bit definitions of the Configuration Register).
Table 4 - Status Register BIT 7 6,5 BIT NAME Receiver Inhibited SYMBOL DESCRIPTION RI This bit, if high, indicates that the receiver is not enabled because either an "Enable Receive to Page fnn" command was never issued, or a packet has been deposited into the RAM buffer page fnn as specified by the last "Enable Receive to Page fnn" command. No messages will be received until this command is issued, and once the message has been received, the RI bit is set, thereby inhibiting the receiver.
Table 5 - Diagnostic Status Register BIT BIT NAME 7 My Reconfiguration MYRECON This bit, if high, indicates that a past reconfiguration was caused by this node. It is set when the Lost Token Timer times out, and should be typically read following an interrupt caused by RECON. Refer to the Improved Diagnostics section for further detail.
DATA COMMAND Table 6 - Command Register DESCRIPTION 0000 0000 Clear Transmit Interrupt This command is used only in the Command Chaining operation. Please refer to the Command Chaining section for definition of this command. 0000 0001 Disable Transmitter This command will cancel any pending transmit command (transmission that has not yet started) and will set the TA (Transmitter Available) status bit to logic "1" when the COM20020 next receives the token.
Table 7 - Address Pointer High Register BIT BIT NAME SYMBOL DESCRIPTION 7 Read Data RDDATA This bit tells the COM20020 whether the following access will be a read or write. A logic "1" prepares the device for a read, a logic "0" prepares it for a write. 6 Auto Increment AUTOINC This bit controls whether the address pointer will increment automatically. A logic "1" on this bit allows automatic increment of the pointer after each access, while a logic "0" disables this function.
Table 9 - Configuration Register BIT BIT NAME SYMBOL DESCRIPTION 7 Reset RESET A software reset of the COM20020 is executed by writing a logic "1" to this bit. A software reset does not reset the microcontroller interface mode, nor does it affect the Configuration Register. The only registers that the software reset affect are the Status Register, the Next ID Register, and the Diagnostic Status Register. This bit must be brought back to logic "0" to release the reset.
Table 10 - Setup Register BIT BIT NAME SYMBOL DESCRIPTION 7 Pulse1 Mode P1MODE This bit determines the type of PULSE1 output driver used in Backplane Mode. When high, a push/pull output is used. When low, an open drain output is used. The default is open drain. 6 Four NACKS FOUR NACKS This bit, when set, will cause the EXNACK bit in the Diagnostic Status Register to set after four NACKs to Free Buffer Enquiry are detected by the COM20020.
Data Register Memory Data Bus I/O Address 04H 2K x 8 INTERNAL RAM 8 D0-D7 Address Pointer Register I/O Address 02H I/O Address 03H High Low Memory Address Bus 11-Bit Counter 11 FIGURE 7 - SEQUENTIAL ACCESS OPERATION 31
INTERNAL RAM continued until the entire packet is read out of RAM. Refer to Figure 7 for an illustration of the Sequential Access operation. When switching between reads and writes, the pointer must first be written with the starting address. At least one cycle time should separate the pointer being loaded and the first read (see timing parameters). The integration of the 2K x 8 RAM in the COM20020 represents significant real estate savings.
• The pointer may now be read to determine how many transfers were completed. If the device is configured to handle both long and short packets (see "Define Configuration" command), then receive pages should always be 512 bytes long because the user never knows what the length of the receive packet will be. In this case, the transmit pages may be made 256 bytes long, leaving at least 512 bytes free at any given time.
ADDRESS 0 SHORT PACKET FORMAT LONG PACKET FORMAT SID ADDRESS 0 1 DID 1 DID 2 COUNT = 256-N 2 3 0 COUNT = 512-N NOT USED COUNT SID NOT USED DATA BYTE 1 DATA BYTE 2 COUNT DATA BYTE 1 DATA BYTE 2 DATA BYTE N-1 255 DATA BYTE N DATA BYTE N-1 NOT USED 511 511 DATA BYTE N N = DATA PACKET LENGTH SID = SOURCE ID DID = DESTINATION ID (DID = 0 FOR BROADCASTS) FIGURE 8 - RAM BUFFER PACKET CONFIGURATION 34
the microcontroller may issue the "Enable Transmit from Page fnn" command, which resets the TA and TMA bits to logic "0". If the message is not a BROADCAST, the COM20020 automatically sends a FREE BUFFER ENQUIRY to the destination node in order to send the message. At this point, one of four possibilities may occur. buffer address 2 contains a zero or non-zero value. The format of the buffer is shown in Figure 8.
The third possibility which may occur after a FREE BUFFER ENQUIRY is issued is if the destination node does not respond at all. In this case, the TA bit is set to a logic "1", while the TMA bit remains at a logic "0". The user should determine whether the node should try to reissue the transmit command. microcontroller will be interrupted if the corresponding bit in the Interrupt Mask Register is set to logic "1". Otherwise, the microcontroller must periodically check the Status Register.
MSB TRI LSB RI TA POR TEST TRI RECON TMA TTA TMA TTA FIGURE 9 - COMMAND CHAINING STATUS REGISTER QUEUE • Up to two outstanding transmit interrupts and two outstanding receive interrupts are COMMAND CHAINING stored by the device, along with their respective status bits. The Command Chaining operation allows consecutive transmissions and receptions to occur without host microcontroller intervention.
In the Command Chaining Mode, at any time after the first command is issued, the processor can issue a second "Enable Transmit from Page fnn" command. The COM20020 stores the fact that the second transmit command was issued, along with the page number. the Status Register will again be updated with the results of the second transmission and a second interrupt resulting from the second transmission will occur.
the status of the receive operation is double buffered in order to retain the results of the first reception for analysis by the processor, therefore the information will remain in the Status Register until the "Clear Receive Interrupt" command is issued. Note that the interrupt will remain active until the "Clear Receive Interrupt" command is issued, and the second interrupt will be stored until the first interrupt is acknowledged.
Bus Determination node to join the network. Once the node joins the network, a reconfiguration occurs, as usual, thus setting the MYRECON bit of the Diagnostic Status Register. Writing to and reading from an odd address location from the COM20020's address space causes the COM20020 to determine the appropriate bus interface. When the COM20020 is powered on the internal registers may be written to.
node with the same ID does not exist on the network. Once it is determined that the ID in the Node ID Register is unique, the software should write a logic "1" to bit 5 of the Configuration Register to enable the basic transmit function. This allows the node to join the network. incorrectly, there is noise on the network, or a reconfiguration is occurring. RCVACT=0, TOKEN=0, TXEN=1: No receive activity is seen and the basic transmit function is enabled.
network. This feature is useful because it minimizes the need for human intervention. When a value placed in the Tentative ID Register matches the Node ID of another node on the network, the TENTID bit is set, telling the software that this NODE ID already exists on the network. The software should periodically place values in the Tentative ID Register and monitor the New Next ID bit to maintain an updated network map.
OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range........................................................................................ 0oC to +70oC Storage Temperature Range...................................................................................... -55oC to +150oC Lead Temperature (soldering, 10 seconds) .............................................................................. +325 oC Positive Voltage on any pin, with respect to ground .......................
PARAMETER Low Output Voltage 1 (nPULSE1 in Normal Mode, nPULSE2, nTXEN) High Output Voltage 1 (nPULSE1 in Normal Mode, nPULSE2, nTXEN) Low Output Voltage 2 (D0-D7) High Output Voltage 2 (D0-D7) Low Output Voltage 3 (nINTR) High Output Voltage 3 (nINTR) SYMBOL MIN TYP VOL1 VOH1 0.4 V ISINK=4mA V ISOURCE=-2mA V ISINK=16mA V ISOURCE=-12mA V ISINK=24mA V ISOURCE=-10mA ISINK=48mA Open Drain Driver 0.4 2.4 VOL3 VOH3 UNIT 2.4 VOL2 VOH2 MAX 0.8 2.
CAPACITANCE (TA = 25°C; fC = 1MHz; VDD = 0V) Output and I/O pins capacitive load specified as follows: PARAMETER SYMBOL MIN TYP MAX UNIT CIN 5.0 pF COUT1 45 pF COUT2 400 pF Input Capacitance Output Capacitance 1 (All outputs except nPULSE1 in BackPlane Mode) Output Capacitance 2 (nPULSE1, in BackPlane Mode Only - Open Drain) COMMENT Maximum Capacitive Load which can be supported by each output. AC Measurements are taken at the following points: Inputs: Outputs: t t 2.0V 2.4V 1.4V 50% 0.
TIMING DIAGRAMS AD0-AD2, D3-D7 VALID t1 VALID DATA t2, t4 nCS t3 ALE t6 t7 t5 nDS t8 t9 DIR t10 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 min Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nDS Low nDS Low to Valid Data nDS High to Data High Impedance Cycle Time (nDS Low to Next Time Low) DIR Setup to nDS Active DIR Hold from nDS Inactive max 30 10 10 20 15 0 4T* 10 10 40 20 units nS nS nS nS nS nS nS nS nS nS * T is the Arbitration Cl
AD0-AD2, D3-D7 VALID t1 VALID DATA t2, t4 nCS t3 ALE t6 nRD t7 t5 t8 Parameter t1 t2 t3 t4 t5 t6 t7 t8 min Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nRD Low nRD Low to Valid Data nRD High to Data High Impedance Cycle Time (nRD Low to Next Time Low) 30 10 10 20 15 0 4T* max 40 20 units nS nS nS nS nS nS nS nS * T is the Arbitration Clock Period.
AD0-AD2, D3-D7 VALID t1 VALID DATA t2, t4 nCS t3 ALE t7 t5 nDS t6 Note 2 t8** t8 DIR t10 t9 min Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nDS Low Valid Data Setup to nDS High Data Hold from nDS High Cycle Time (nDS Low to Next Time Low)** DIR Setup to nDS Active DIR Hold from nDS Inactive 30 10 10 20 15 30 10 4T* 10 10 max units nS nS nS nS nS nS nS nS nS nS * T is the Arbitration Clock Peri
AD0-AD2, D3-D7 VALID t1 VALID DATA t2, t4 nCS t3 ALE t7 t5 nWR t6 Note 2 t8** t8 min Parameter t1 t2 t3 t4 t5 t6 t7 t8 Address Setup to ALE Low Address Hold from ALE Low nCS Setup to ALE Low nCS Hold from ALE Low ALE Low to nWR Low Valid Data Setup to nWR High Data Hold from nWR High Cycle Time (nWR Low to Next Time Low)** 30 10 10 20 15 30 10 4T* max units nS nS nS nS nS nS nS nS * T is the Arbitration Clock Period.
A0-A2 VALID t1 t2 nCS t4 t3 t5 nRD t7 t6 D0-D7 VALID DATA Parameter t1 t2 t3 t4 t5 t6 t7 min Address Setup to nRD Active Address Hold from nRD Inactive nCS Setup to nRD Active nCS Hold from nRD Inactive Cycle Time (nRD Low to Next Time Low) nRD Low to Valid Data nRD High to Data High Impedance max units 40 20 nS nS nS nS nS nS nS 15 10 5** 0 4T* 0 * T is the Arbitration Clock Period.
A0-A2 VALID t1 t2 nCS t4 t3 DIR t7 t5 t6 nDS t8 t9 D0-D7 VALID DATA min Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 * Address Setup to nDS Active Address Hold from nDS Inactive nCS Setup to DS Active nCS Hold from DS Inactive DIR Setup to nDS Active Cycle Time (nDS Low to Next Time Low) DIR Hold from nDS Active nDS Low to Valid Data nDS High to Data High Impedence max units 40 20 nS nS nS nS nS nS nS nS nS 15 10 5** 0 10 4T* 10 0 T is the Arbitration Clock Period.
A0-A2 VALID t1 t2 nCS t4 t3 t5 nWR t6 D0-D7 Note 2 t5** t7 VALID DATA Parameter t1 t2 t3 t4 t5 t6 t7 Address Setup to nWR Active Address Hold from nWR Inactive nCS Setup to WR Active nCS Hold from nWR Inactive Cycle Time (nWR Low to Next Time Low)** Valid Data Setup to nWR High Data Hold from nWR High min 15 10 5 0 4T* 30** 10 max units nS nS nS nS nS nS nS * T is the Arbitration Clock Period.
A0-A2 VALID t1 t2 nCS t4 t3 DIR t5 t7 t6 nDS t8 D0-D7 Note 2 t6** t9 VALID DATA t1 t2 t3 t4 t5 t6 t7 t8 t9 Parameter Address Setup to nDS Active Address Hold from nDS Inactive nCS Setup to nDS Active nCS Hold from nDS Inactive DIR Setup to nDS Active Cycle Time (nDS Low to Next Time Low)** DIR Hold from nDS Inactive Valid Data Setup to nDS High Data Hold from nDS High min 15 10 5 0 10 4T* 10 30** 10 max units nS nS nS nS nS nS nS nS nS * T is the Arbitration Clock Period.
nTXEN t4 t5 t2 t1 nPULSE1 LAST BIT (400 nS BIT TIME) t3 t2 t1 nPULSE2 t6 RXIN t7 Parameter t1 t2 t3 t4 t5 t6 t7 min nPULSE1, nPULSE2 Pulse Width nPULSE1, nPULSE2 Period nPULSE1, nPULSE2 Overlap nTXEN Low to nPULSE1 Low** Beginning of Last Bit Time to nTXEN High** RXIN Pulse Width RXIN Period -10 850 250 10 typ 100 * 400 * 0 max units +10 950 350 nS nS nS nS nS nS nS 100* 400 * * t1 = 2 x (crystal period) for clock frequencies other than 20 MHz.
nTXEN t1 t3 nPULSE1 t2 t9 LAST BIT (400 nS BIT TIME) t4 t5 nPULSE2 (Internal Clk) t8 t6 t7 t10 RXIN t11 Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 min nPULSE2 High to nTXEN Low nPULSE1 Pulse Width nPULSE1 Period nPULSE2 Low to nPULSE1 Low nPULSE2 High Time nPULSE2 Low Time nPULSE2 Period nPULSE2 High to nTXEN High (First rising edge on nPULSE2 after Last Bit Time) nTXEN Low to first nPULSE1 Low** t10 t11 typ 0 max 50 0 50 nS nS nS nS nS nS nS nS 650 750 nS 200* 400* -25 25 100* 100* 200* 10
t1 t3 t2 XTAL1 t1 t2 t3 t4 Input Input Input Input Parameter min Clock High Time Clock Low Time Clock Period Clock Frequency 20 20 50 10 typ max units 100 20 nS nS nS MHz FIGURE 16 - TTL INPUT TIMING ON XTAL1 PIN t1 nRESET IN nINTR t2 Parameter t1 t2 min nRESET IN Pulse Width nINTR High to Next nINTR Low typ 3.
G PIN NO. 1 E J A F B B1 D3 D2 R J J D1 D C DIM A A1 B B1 C D D1 D2 D3 E F G J R Seating Plane Base Plane A1 28L .160-.180 .090-.120 .013-.021 .026-.032 .020-.045 .485-.495 .450-.456 .390-.430 .300 REF .050 BSC .042-.056 .042-.048 .000-.020 .025-.045 NOTES: 1. All dimensions are in inches. 2. Circle indicating pin 1 can appear on a top surface as shown on the drawing or right above it on a beveled edge.
E1 E C eA D e B A2 Base Plane A A1 Seating Plane L B1 S e B 24L .090-.150 .020-.065 .145-.155 .016-.021 .060-.070 .010-.014 1.245-1.265 .590-.630 .530-.545 .100BSC .600REF .610-.670 .120-.140 .065-.085 DIM A A1 A2 B B1 C D E E1 e eA eB L S Note: All dimensions are in inches.
COM20020 ERRATA SHEET PAGE SECTION/FIGURE/ENTRY CORRECTION DATE REVISED 5 Pin No.
STANDARD MICROSYSTEMS CORP. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies.