- Standard Microsystems Ethernet Transceiver Specification Sheet

ManualsBrandsSMSC ManualsSwitchFlexPWR LAN8720

SMSC LAN8720/LAN8720i Revision 1.0 (05-28-09)

DATASHEET

Datasheet

PRODUCT FEATURES

LAN8720/LAN8720i

Small Footprint RMII 10/100

Ethernet Transceiver with HP

Auto-MDIX Support

Highlights

 Single-Chip Ethernet Physical Layer Transceiver

(PHY)

 Comprehensive flexPWR

Technology

— Flexible Power Management Architecture

— Power savings of up to 40% compared to competition

— LVCMOS Variable I/O voltage range: +1.6V to +3.6V

— Integrated 1.2V regulator

 HP Auto-MDIX support

 Miniature 24 pin QFN lead-free RoHS compliant

package (4 x 4 x 0.85mm height).

Target Applications

 Set-Top Boxes

 Networked Printers and Servers

 Test Instrumentation

 LAN on Motherboard

 Embedded Telecom Applications

 Video Record/Playback Systems

 Cable Modems/Routers

 DSL Modems/Routers

 Digital Video Recorders

 IP and Video Phones

 Wireless Access Points

 Digital Televisions

 Digital Media Adaptors/Servers

 Gaming Consoles

 POE Applications

Key Benefits

 High-Performance 10/100 Ethernet Transceiver

— Compliant with IEEE802.3/802.3u (Fast Ethernet)

— Compliant with ISO 802-3/IEEE 802.3 (10BASE-T)

— Loop-back modes

— Auto-negotiation

— Automatic polarity detection and correction

— Link status change wake-up detection

— Vendor specific register functions

 Power and I/Os

— Various low power modes

— Integrated power-on reset circuit

— Two status LED outputs

— Latch-Up Performance Exceeds 150mA per EIA/JESD

78, Class II

— May be used with a single 3.3V supply

 Advanced Features

— Able to use a low cost 25Mhz crystal for the lowest

eBOM

 Packaging

— 24-pin QFN (4x4 mm) Lead-Free RoHS Compliant

package with RMII

 Environmental

— Extended Commercial Temperature Range (0°C to

+85°C)

— Industrial Temperature Range (-40°C to +85°C) version

available (LAN8720i)

Summary of content (79 pages)

PAGE 1
LAN8720/LAN8720i Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support PRODUCT FEATURES Datasheet Highlights Single-Chip Ethernet Physical Layer Transceiver (PHY) Comprehensive flexPWR® Technology — — — — Key Benefits — — — — — — — Flexible Power Management Architecture Power savings of up to 40% compared to competition LVCMOS Variable I/O voltage range: +1.6V to +3.6V Integrated 1.
PAGE 2
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet ORDER NUMBER(S): LAN8720A-CP-TR FOR 24-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO +85°C TEMP) LAN8720Ai-CP-TR FOR 24-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (-40 TO +85°C TEMP) Reel Size is 4000 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2009 SMSC or its subsidiaries. All rights reserved.
PAGE 3
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table of Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 1.2 1.3 General Terms and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 4.8 4.9 4.10 4.11 4.12 4.13 4.14 Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.1 Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8.2 Re-starting Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Chapter 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SMSC LAN8720/LAN8720i 5 DATASHEET Revision 1.
PAGE 6
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet List of Figures Figure 1.1 Figure 1.2 Figure 2.1 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 4.7 Figure 4.8 Figure 4.9 Figure 4.10 Figure 4.11 Figure 5.1 Figure 5.2 Figure 5.3 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Figure 6.8 Figure 6.9 Figure 6.10 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 9.1 Figure 9.1 Figure 9.
PAGE 7
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet List of Tables Table 2.1 LAN8720/LAN8720i 24-PIN QFN Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.2 RMII Signals 24-QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 8
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 6.2 100M RMII Receive Timing Values (50MHz REF_CLK IN). . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.3 100M RMII Transmit Timing Values (50MHz REF_CLK IN) . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.4 10M RMII Receive Timing Values (50MHz REF_CLK IN). . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.5 10M RMII Transmit Timing Values (50MHz REF_CLK IN) . . . . . . . . . . .
PAGE 9
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 1 Introduction 1.1 General Terms and Conventions The following is list of the general terms used in this document: BYTE 8-bits FIFO First In First Out buffer; often used for elasticity buffer MAC Media Access Controller MII Media Independent Interface RMIITM Reduced Media Independent InterfaceTM N/A Not Applicable X Indicates that a logic state is “don’t care” or undefined.
PAGE 10
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 10/100 Ethernet MAC MDI Transformer RJ45 LAN8720 Ethernet Transceiver RMII MODE LED Status Crystal or Clock Osc Figure 1.1 LAN8720/LAN8720i System Block Diagram 1.3 Architectural Overview The LAN8720/LAN8720i is compliant with IEEE 802.3-2005 standards (RMII Pins tolerant to 3.6V) and supports both IEEE 802.3-2005 compliant and vendor-specific register functions.
PAGE 11
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet MODE0 MODE1 MODE2 nRST MODE Control AutoNegotiation 10M Tx Logic Reset Control SMI 10M Transmitter HP Auto-MDIX TXP / TXN Transmit Section 100M Tx Logic Management Control RXP / RXN 100M Transmitter MDIX Control TXD[1:0] TXEN RXER RMII Logic RXD[1:0] 100M Rx Logic DSP System: Clock Data Recovery Equalizer XTAL2 Interrupt Generator nINT 100M PLL Receive Section LED Circuitry 10M Rx Logic Squelch & F
PAGE 12
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 2 Pin Configuration VDD2A 1 LED2/nINTSEL 2 LED1/REGOFF 3 XTAL2 4 XTAL1/CLKIN 5 VDDCR 6 TXP TXN VDD1A 19 RXN 22 20 RXP 21 RBIAS 23 Package Pin-out Diagram and Signal Table 24 2.1 SMSC LAN8720/ LAN8720i 24 PIN QFN (Top View) 18 TXD1 17 TXD0 16 TXEN 15 nRST 14 nINT/REFCLKO 13 MDC 10 11 12 RXER/PHYAD0 MDIO 9 VDDIO CRS_DV/MODE2 8 7 RXD1/MODE1 RXD0/MDE0 VSS Figure 2.
PAGE 13
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 2.1 LAN8720/LAN8720i 24-PIN QFN Pinout PIN NO. PIN NAME PIN NO. PIN NAME 1 VDD2A 13 MDC 2 LED2/nINTSEL 14 nINT/REFCLKO 3 LED1/REGOFF 15 nRST 4 XTAL2 16 TXEN 5 XTAL1/CLKIN 17 TXD0 6 VDDCR 18 TXD1 7 RXD1/MODE1 19 VDD1A 8 RXD0/MODE0 20 TXN 9 VDDIO 21 TXP 10 RXER/PHYAD0 22 RXN 11 CRS_DV/MODE2 23 RXP 12 MDIO 24 RBIAS SMSC LAN8720/LAN8720i 13 DATASHEET Revision 1.
PAGE 14
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 3 Pin Description This chapter describes the signals on each pin. When a lower case “n” is used at the beginning of the signal name, it indicates that the signal is active low. For example, nRST indicates that the reset signal is active low. The buffer type for each signal is indicated in the TYPE column, and a description of the buffer types is provided in Table 3.1. Table 3.
PAGE 15
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 3.1 MAC Interface Signals Table 3.2 RMII Signals 24-QFN SIGNAL NAME 24-QFN PIN # TYPE DESCRIPTION TXD0 17 I8 Transmit Data 0: The MAC transmits data to the PHY using this signal in all modes. TXD1 18 I8 Transmit Data 1: The MAC transmits data to the PHY using this signal in all modes TXEN 16 IPD Transmit Enable: Indicates that valid data is presented on the TXD[1:0] signals, for transmission.
PAGE 16
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 3.3 LED Signals 24-QFN (continued) SIGNAL NAME 24-QFN PIN # TYPE LED2/ nINTSEL 2 IOPU DESCRIPTION LED2 – Link speed LED Indication. See Section 5.3.7 for a description of LED modes. nINTSEL: On power-up or external reset, the mode of the nINT/REFCLKO pin is selected. See Section 4.10 for additional detail.
PAGE 17
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 3.5 10/100 Line Interface Signals Table 3.6 10/100 Line Interface Signals 24-QFN SIGNAL NAME 24-QFN PIN # TYPE TXP 21 AIO Transmit/Receive Positive Channel 1. TXN 20 AIO Transmit/Receive Negative Channel 1. RXP 23 AIO Transmit/Receive Positive Channel 2. RXN 22 AIO Transmit/Receive Negative Channel 2. 3.6 DESCRIPTION Analog Reference Table 3.
PAGE 18
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 4 Architecture Details 4.
PAGE 19
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 4.2.2 4B/5B Encoding The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from 4-bit nibbles to 5-bit symbols (known as “code-groups”) according to Table 4.1. Each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for control information or are not valid.
PAGE 20
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 4.
PAGE 21
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 4.2.6 100M Phase Lock Loop (PLL) The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. PLL MAC Ref_CLK RMII 25MHz by 4 bits 4B/5B Encoder NRZI Converter NRZI MLT-3 Converter MLT-3 MLT-3 Magnetics RMII 50Mhz by 2 bits 125 Mbps Serial MLT-3 RJ45 25MHz by 5 bits Scrambler and PISO Tx Driver MLT-3 CAT-5 Figure 4.
PAGE 22
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 4.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. 4.3.4 Descrambling The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. During reception of IDLE (/I/) symbols.
PAGE 23
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet CLEAR-TEXT J K 5 5 5 D data data data data T R 5 5 5 5 5 D data data data data Idle RX_CLK RX_DV RXD Figure 4.3 Relationship Between Received Data and Specific MII Signals 4.3.8 Receiver Errors During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0 through F), and the /T/R/ (ESD) symbol pair.
PAGE 24
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet In order to comply with legacy 10Base-T MAC/Controllers, in Half-duplex mode the transceiver loops back the transmitted data, on the receive path. This does not confuse the MAC/Controller since the COL signal is not asserted during this time. The transceiver also supports the SQE (Heartbeat) signal. See Section 5.3.2, "Collision Detect," on page 50, for more details.
PAGE 25
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 4.5.3 10M Receive Data Across the MII/RMII Interface For MII, the 4 bit data nibbles are sent to the MII block. In MII mode, these data nibbles are valid on the rising edge of the 2.5 MHz RXCLK. For RMII, the 2bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid on the rising edge of the RMII REF_CLK. 4.5.
PAGE 26
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet CRS_DV toggles at 25 MHz in 100Mb/s mode and 2.5 MHz in 10Mb/s mode when CRS ends before RXDV (i.e. the FIFO still has bits to transfer when the carrier event ends.) Therefore, the MAC can accurately recover RXDV and CRS. During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data on RXD[1:0] is considered valid once CRS_DV is asserted.
PAGE 27
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 4.7.1 REF_CLK In Mode A 50MHz source of REF_CLK must be available external to the LAN8720 when using this mode. The clock is driven to both the MAC and PHY as shown in Figure 4.4.
PAGE 28
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet nINT not available in this configuration MAC RMII MDIO MDC Capable of accepting 50MHz clock TXD[1:0] LAN8720 10/100 PHY 24-QFN RMII 2 TXEN Mag RXD[1:0] RJ45 TXP 2 TXN CRS_DV RXER REF_CLK RXP RXN REFCLKO XTAL1/CLKIN LED[2:1] 25MHz 2 XTAL2 nRST Interface Figure 4.5 LAN8720 sources REF_CLK from a 25MHz crystal In some system architectures, a 25MHz clock source is available.
PAGE 29
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet example, only a 25MHz clock can be used (clock cannot be 50MHz). Similar to the 25MHz crystal mode, the nINT function is disabled. nINT not available in this configuration MAC RMII LAN8720 10/100 PHY 24-QFN RMII MDIO MDC Capable of accepting 50MHz clock TXD[1:0] Mag 2 RJ45 TXP TXEN TXN RXD[1:0] RXP 2 RXN CRS_DV RXER REF_CLK REFCLKO XTAL1/CLKIN LED[2:1] 25MHz Clock 2 XTAL2 nRST Interface Figure 4.
PAGE 30
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 100M ADC (analog) 100M PLL (analog) 100M equalizer/BLW/clock recovery (DSP) 10M SQUELCH (analog) 10M PLL (analog) 10M Transmitter (analog) When enabled, auto-negotiation is started by the occurrence of one of the following events: Hardware reset Software reset Power-down reset Link status down Setting register 0, bit 9 high (auto-negotiation restart) On detection of one of these
PAGE 31
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 4.8.1 Parallel Detection If the LAN8720/LAN8720i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be Half Duplex per the IEEE standard. This ability is known as “Parallel Detection.
PAGE 32
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Figure 4.7 Direct Cable Connection vs. Cross-over Cable Connection 4.10 nINTSEL Strapping and LED Polarity Selection The LED2/nINTSEL pin is used to select between one of two available modes: REF_CLK In Mode and REF_CLK Out Mode. The configured mode determines the function of the nINT/REFCLK0 pin. Table 4.
PAGE 33
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet nINTSEL = 1 LED output = active low nINTSEL = 0 LED output = active high VDD2A LED2/nINTSEL 10K ~270 ohms ~270 ohms LED2/nINTSEL Figure 4.8 nINTSEL Strapping on LED2 4.11 REGOFF and LED Polarity Selection The REGOFF configuration pin is shared with the LED1 pin. The LED1 output will automatically change polarity based on the presence of an external pull-up resistor.
PAGE 34
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 4.12 PHY Address Strapping The PHY ADDRESS bit is latched into an internal register at the end of a hardware reset. The address bit is input on the RXER/PHYAD0 pin. The default setting is PHYAD0=0 as described in Section 5.3.9.1. 4.13 Variable Voltage I/O The Digital I/O pins on the LAN8720/LAN8720i are variable voltage to take advantage of low power savings from shrinking technologies.
PAGE 35
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Read Cycle MDC MDI0 32 1's Preamble 0 1 Start of Frame 1 0 OP Code A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 PHY Address Register Address D15 D14 Turn Around ... ... D1 D0 Data Data To Phy Data From Phy Figure 4.
PAGE 36
Table 5.1 Control Register: Register 0 (Basic) 15 14 13 12 11 10 9 8 7 6 Reset Loopback Speed Select A/N Enable Power Down Isolate Restart A/N Duplex Mode Collision Test 5 4 3 2 1 0 Reserved Table 5.
PAGE 37
15 14 13 12 11 Next Page Reserved Remote Fault Reserved 10 Pause Operation 9 8 7 6 5 4 100BaseT4 100BaseTX Full Duplex 100BaseTX 10BaseT Full Duplex 10BaseT 3 2 1 0 IEEE 802.3 Selector Field Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended) 14 13 12 Next Page Acknowledge Remote Fault 11 Reserved 10 9 8 7 6 5 4 Pause 100BaseT4 100Base-TX Full Duplex 100BaseTX 10Base-T Full Duplex 10BaseT 3 2 1 0 IEEE 802.
PAGE 38
1 5 14 RSVD 13 12 11 10 9 8 EDPWRDOWN RSVD LOWSQEN MDPREBP FARLOOPBACK 7 RSVD 6 5 ALTINT 4 RSVD 3 2 1 0 PHYADBP Force Good Link Status ENERGYON RSVD RSVD = Reserved Table 5.11 Special Modes Register 18: Vendor-Specific 15 14 13 Reserved MIIMODE 12 11 10 9 8 7 6 Reserved 5 4 3 2 MODE 1 0 PHYAD 38 DATASHEET Table 5.12 Register 24: Vendor-Specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 4 3 2 1 0 Reserved Table 5.
PAGE 39
Datasheet 15 14 13 12 11 10 AMDIXCTRL Reserved CH_SELECT Reserved SQEOFF 9 8 7 6 5 4 Reserved 3 2 XPOL 1 0 Reserved Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 5.17 Interrupt Source Flags Register 29: Vendor-Specific 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 Reserved Table 5.
PAGE 40
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet The following registers are supported (register numbers are in decimal): Table 5.20 SMI Register Mapping REGISTER # 5.
PAGE 41
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 5.21 Register 0 - Basic Control ADDRESS NAME DESCRIPTION MODE DEFAULT 0.15 Reset 1 = software reset. Bit is self-clearing. For best results, when setting this bit do not set other bits in this register. The configuration (as described in Section 5.3.9.2) is set from the register bit values, and not from the mode pins. RW/ SC 0 0.14 Loopback 1 = loopback mode, 0 = normal operation RW 0 0.
PAGE 42
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 5.22 Register 1 - Basic Status (continued) ADDRESS NAME DESCRIPTION 1.4 Remote Fault 1.3 Auto-Negotiate Ability 1.2 Link Status 1.1 Jabber Detect 1.
PAGE 43
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 5.25 Register 4 - Auto Negotiation Advertisement (continued) ADDRESS NAME 4.9 100Base-T4 4.8 100Base-TX Full Duplex 4.7 100Base-TX 4.6 10Base-T Full Duplex 4.5 4.4:0 DESCRIPTION MODE DEFAULT 1 = T4 able, 0 = no T4 ability This Phy does not support 100Base-T4.
PAGE 44
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 5.27 Register 6 - Auto Negotiation Expansion ADDRESS NAME 6.15:5 Reserved 6.4 Parallel Detection Fault 6.3 DESCRIPTION MODE DEFAULT RO 0 1 = fault detected by parallel detection logic 0 = no fault detected by parallel detection logic RO/ LH 0 Link Partner Next Page Able 1 = link partner has next page ability 0 = link partner does not have next page ability RO 0 6.
PAGE 45
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 5.29 Register 17 - Mode Control/Status (continued) ADDRESS NAME DESCRIPTION MODE DEFAULT 17.6 ALTINT Alternate Interrupt Mode. 0 = Primary interrupt system enabled (Default). 1 = Alternate interrupt system enabled. See Section 5.2, "Interrupt Management," on page 48. RW 0 17.5:4 Reserved Write as 0, ignore on read. RW 00 17.3 PHYADBP 1 = PHY disregards PHY address in SMI access write. RW 0 17.
PAGE 46
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 5.32 Register 27 - Special Control/Status Indications ADDRESS NAME DESCRIPTION MODE DEFAULT 27.15 AMDIXCTRL HP Auto-MDIX control 0 - Auto-MDIX enable 1 - Auto-MDIX disabled (use 27.13 to control channel) RW 0 27.14 Reserved Reserved RW 0 27.13 CH_SELECT Manual Channel Select 0 - MDI -TX transmits RX receives 1 - MDIX -TX receives RX transmits RW 0 27.12 Reserved Write as 0. Ignore on read.
PAGE 47
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 5.34 Register 29 - Interrupt Source Flags (continued) ADDRESS NAME 29.1 INT1 29.0 Reserved DESCRIPTION MODE DEFAULT 1 = Auto-Negotiation Page Received 0 = not source of interrupt RO/ LH X Ignore on read. RO/ LH 0 MODE DEFAULT Table 5.35 Register 30 - Interrupt Mask ADDRESS NAME DESCRIPTION 30.15:8 Reserved Write as 0; ignore on read. RO 0 30.
PAGE 48
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 5.2 Interrupt Management The Management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. It generates an active low asynchronous interrupt signal on the nINT output whenever certain events are detected as setup by the Interrupt Mask Register 30. The Interrupt system on the SMSC The LAN8720 has two modes, a Primary Interrupt mode and an Alternative Interrupt mode.
PAGE 49
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Note: The ENERGYON bit 17.1 is defaulted to a ‘1’ at the start of the signal acquisition process, therefore the Interrupt source flag 29.7 will also read as a ‘1’ at power-up. If no signal is present, then both 17.1 and 29.7 will clear within a few milliseconds. 5.2.2 Alternate Interrupt System The Alternative method is enabled by writing a ‘1’ to 17.6 (ALTINT).
PAGE 50
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet in repeater mode or full-duplex mode. Otherwise the transceiver asserts CRS based on either transmit or receive activity. The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span.
PAGE 51
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 5.3.5.1 General Power-Down This power-down is controlled by register 0, bit 11. In this mode the entire transceiver, except the management interface, is powered-down and stays in that condition as long as bit 0.11 is HIGH. When bit 0.11 is cleared, the transceiver powers up and is automatically reset. 5.3.5.2 Energy Detect Power-Down This power-down mode is activated by setting bit 17.13 to 1.
PAGE 52
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 5.3.8.1 Near-end Loopback Near-end loopback is a mode that sends the digital transmit data back out the receive data signals for testing purposes as indicated by the blue arrows in Figure 5.1.The near-end loopback mode is enabled by setting bit register 0 bit 14 to logic one.
PAGE 53
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet transmit signals an the output of the transformer back to the receiver inputs, and this loopback will work at both 10 and 100. 10/100 Ethernet MAC TXD 1 2 3 4 5 6 7 8 TX RXD RX Digital XFMR Analog SMSC RJ45 Loopback Cable. Created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6. Ethernet Transceiver Figure 5.3 Connector Loopback Block Diagram 5.3.
PAGE 54
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 5.39 MODE[2:0] Bus DEFAULT REGISTER BIT VALUES MODE[2:0] MODE DEFINITIONS REGISTER 0 REGISTER 4 [13,12,10,8] [8,7,6,5] 000 10Base-T Half Duplex. Auto-negotiation disabled. 0000 N/A 001 10Base-T Full Duplex. Auto-negotiation disabled. 0001 N/A 010 100Base-TX Half Duplex. Auto-negotiation disabled. CRS is active during Transmit & Receive. 1000 N/A 011 100Base-TX Full Duplex.
PAGE 55
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 6 AC Electrical Characteristics The timing diagrams and limits in this section define the requirements placed on the external signals of the Phy. 6.1 Serial Management Interface (SMI) Timing The Serial Management Interface is used for status and control as described in Section 4.14. T1.1 Clock MDC T1.2 Data Out MDIO Valid Data (Read from PHY) T1.3 Data In MDIO T1.4 Valid Data (Write to PHY) Figure 6.
PAGE 56
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.2 RMII 10/100Base-TX/RX Timings (50MHz REF_CLK IN) The 50MHz REF_CLK IN timing applies to the case when nINTSEL is floated or pulled-high on the LAN8720. In this mode, a 50MHz clock must be provided to the LAN8720 CLKIN pin. For more information on REF_CLK IN Mode, see Section 4.7.1. 6.2.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK IN) 6.2.1.1 100M RMII Receive Timing (50MHz REF_CLK IN) Clock In CLKIN T6.
PAGE 57
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.2.1.2 100M RMII Transmit Timing (50MHz REF_CLK IN) Clock In CLKIN T8.1 Data In TXD[1:0] TX_EN T8.2 Valid Data Figure 6.3 100M RMII Transmit Timing Diagram (50MHz REF_CLK IN) Table 6.3 100M RMII Transmit Timing Values (50MHz REF_CLK IN) PARAMETER DESCRIPTION MIN T8.1 Transmit signals required setup to rising edge of CLKIN 4 ns T8.
PAGE 58
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.2.2 RMII 10Base-T TX/RX Timings (50MHz REF_CLK IN) 6.2.2.1 10M RMII Receive Timing (50MHz REF_CLK IN) Clock In CLKIN T9.1 Data Out RXD[1:0] CRS_DV Valid Data Figure 6.4 10M RMII Receive Timing Diagram (50MHz REF_CLK IN) Table 6.4 10M RMII Receive Timing Values (50MHz REF_CLK IN) PARAMETER DESCRIPTION MIN T9.
PAGE 59
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.2.2.2 10M RMII Transmit Timing (50MHz REF_CLK IN) Clock In CLKIN T 10.2 T 10.1 Data In TXD[1:0] TX_EN Valid Data Figure 6.5 10M RMII Transmit Timing Diagram (50MHz REF_CLK IN) Table 6.5 10M RMII Transmit Timing Values (50MHz REF_CLK IN) PARAMETER DESCRIPTION MIN TYP T10.1 Transmit signals required setup to rising edge of CLKIN 4 ns T10.
PAGE 60
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.3 RMII 10/100Base-TX/RX Timings (50MHz REF_CLK OUT) The 50MHz REF_CLK OUT timing applies to the case when LED/nINTSEL is pulled-low on the LAN8720. In this mode, a 25MHz crystal or clock oscillator must be provided to the LAN8720. For more information on 50MHz REF_CLK OUT mode, see Section 4.7.2 6.3.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK OUT) 6.3.1.1 100M RMII Receive Timing (50MHz REF_CLK OUT) REFCLKO T11.
PAGE 61
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.3.1.2 100M RMII Transmit Timing (50MHz REF_CLK OUT) REFCLKO T12.1 Data In TXD[1:0] TX_EN T12.2 Valid Data Figure 6.7 100M RMII Transmit Timing Diagram (50MHz REF_CLK OUT) Table 6.7 100M RMII Transmit Timing Values (50MHz REF_CLK OUT) PARAMETER DESCRIPTION MIN T12.1 Transmit signals required setup to rising edge of REFCLKO 7 ns T12.2 Transmit signals required hold after rising edge of REFCLKO 2.
PAGE 62
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.3.2 RMII 10Base-T TX/RX Timings (50MHz REF_CLK OUT) 6.3.2.1 10M RMII Receive Timing (50MHz REF_CLK OUT) REFCLKO T13.1 Data Out RXD[1:0] CRS_DV Valid Data Figure 6.8 10M RMII Receive Timing Diagram (50MHz REF_CLK OUT) Table 6.8 10M RMII Receive Timing Values (50MHz REF_CLK OUT) PARAMETER DESCRIPTION MIN T13.1 Output delay from rising edge of REFCLKO to receive signals output valid 1.
PAGE 63
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.3.2.2 10M RMII Transmit Timing (50MHz REF_CLK OUT) REFCLKO T 14.2 T 14.1 Data In TXD[1:0] TX_EN Valid Data Figure 6.9 10M RMII Transmit Timing Diagram (50MHz REF_CLK OUT) Table 6.9 10M RMII Transmit Timing Values (50MHz REF_CLK OUT) PARAMETER DESCRIPTION MIN TYP T14.1 Transmit signals required setup to rising edge of REFCLKO 7 ns T14.2 Transmit signals required hold after rising edge of REFCLKO 2.
PAGE 64
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.5 Reset Timing T 11.1 nRST T 11.2 T 11.3 Configuration Signals T 11.4 O utput drive Figure 6.10 Reset Timing Diagram Table 6.11 Reset Timing Values PARAMETER DESCRIPTION MIN TYP MAX UNITS T11.1 Reset Pulse Width 100 us T11.2 Configuration input setup to nRST rising 200 ns T11.3 Configuration input hold after nRST rising 10 ns T11.4 Output Drive after nRST rising 20 Revision 1.
PAGE 65
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 6.6 Clock Circuit LAN8720/LAN8720i can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. See Table 6.12 for the recommended crystal specifications. Table 6.
PAGE 66
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 7 DC Electrical Characteristics 7.1 DC Characteristics 7.1.1 Maximum Guaranteed Ratings Stresses beyond those listed in may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7.1 Maximum Conditions PARAMETER CONDITIONS MIN TYP MAX UNITS VDD1A, VDD2A, VDDIO Power pins to all other pins. -0.5 +3.
PAGE 67
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet no change in operation or performance due to the event. All pins on the LAN8720 provide +/-5kV HBM protection. 7.1.1.2 IEC61000-4-2 Performance The IEC61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device powered down.
PAGE 68
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 7.4 Power Consumption Device Only (REF_CLK IN MODE) VDDA3.3 POWER PINS(MA) VDDCR POWER PIN(MA) VDDIO POWER PIN(MA) TOTAL CURRENT (MA) TOTAL POWER (MW) Max 27.1 20.4 0.6 48.1 158.7 Typical 25.7 18.5 0.5 44.7 147.5 Min 22.4 17.4 0.3 40.1 95.3 Note 7.1 Max 9.7 13 0.6 23.3 76.9 Typical 8.9 11.8 0.5 21.2 70 Min 8.3 11.1 0.3 19.7 41.3 Note 7.1 Max 4.2 3 0.2 7.4 24.
PAGE 69
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 7.5 Power Consumption Device Only (50MHz REF_CLK OUT MODE) 10BASE-T /W TRAFFIC ENERGY DETECT POWER DOWN GENERAL POWER DOWN Max 9.9 12.8 6.4 29.1 96 Typical 8.8 11.3 5.6 25.7 84.8 Min 7.1 9.7 3 19.8 40.5 Note 7.3 Max 4.5 2.7 0.3 7.5 24.8 Typical 4 1.5 0.2 5.7 18.8 Min 3.9 1.2 0 5.1 14.3 Note 7.3 Max 0.4 2.5 0.2 3.1 10.2 Typical 0.4 1.3 0.2 1.9 6.3 Min 0.4 1 0 1.
PAGE 70
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 7.1.4 DC Characteristics - Input and Output Buffers Table 7.6 RMII Bus Interface Signals NAME VIH (V) VIL (V) IOH IOL VOL (V) VOH (V) TXD0 0.68 * VDDIO 0.4 * VDDIO TXD1 0.68 * VDDIO 0.4 * VDDIO TXEN 0.68 * VDDIO 0.4 * VDDIO TXCLK -8 mA +8 mA +0.4 VDDIO – +0.4 RXD0/MODE0 -8 mA +8 mA +0.4 VDDIO – +0.4 RXD1/MODE1 -8 mA +8 mA +0.4 VDDIO – +0.4 RXER/PHYAD0 -8 mA +8 mA +0.4 VDDIO – +0.
PAGE 71
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 7.7 LAN Interface Signals NAME VIH VIL IOH IOL VOL VOH TXP TXN See Table 7.12, “100Base-TX Transceiver Characteristics,” on page 72 and Table 7.13, “10BASE-T Transceiver Characteristics,” on page 72. RXP RXN Table 7.8 LED Signals NAME VIH (V) VIL (V) IOH IOL VOL (V) VOH (V) LED1/REGOFF 0.63 * VDD2A 0.39 * VDD2A -12 mA +12 mA +0.4 VDD2A – +0.4 LED2/nINTSEL 0.63 * VDD2A 0.
PAGE 72
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Table 7.11 Internal Pull-Up / Pull-Down Configurations (continued) NAME PULL-UP OR PULL-DOWN RXD1/MODE1 Pull-up RXER/PHYAD0 Pull-down CRS_DV/MODE2 Pull-up LED1/REGOFF Pull-down LED2/nINTSEL Pull-up MDIO Pull-up nINT/REFCLKO Pull-up nRST Pull-up Table 7.
PAGE 73
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 8 Application Notes 8.1 Application Diagram The LAN8720 requires few external components. The voltage on the magnetics center tap can range from 2.5 - 3.3V. 8.1.1 RMII Diagram RMII MDIO MDC nINT LAN8720 10/100 PHY 24-QFN RMII Mag RJ45 TXP TXN TXD[1:0] 2 RXP TXEN RXN RXD[1:0] 2 RXER XTAL1/CLKIN LED[2:1] 25MHz 2 XTAL2 nRST Interface Figure 8.
PAGE 74
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 8.1.2 Power Supply Diagram Analog Supply 3.3V Power to magnetics interface. 6 LAN8720 24-QFN 19 VDD1A VDDCR 1uF CBYPASS VDDDIO Supply 1.8 - 3.3V 9 VDDIO 1 VDD2A CBYPASS CBYPASS CF R 15 24 RBIAS nRST C 12k VSS Figure 8.3 High-Level System Diagram for Power 8.1.3 Twisted-Pair Interface Diagram LAN8720 24-QFN 49.9 Resistors Analog Supply 3.3V VDD2A Magnetic Supply 2.5 - 3.
PAGE 75
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet 8.2 Magnetics Selection For a list of magnetics selected to operate with the SMSC LAN8720, please refer to the Application note “AN 8-13 Suggested Magnetics”. http://www.smsc.com/main/appnotes.html#Ethernet%20Products SMSC LAN8720/LAN8720i 75 DATASHEET Revision 1.
PAGE 76
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 9 Package Outline Figure 9.1 LAN8720/LAN8720i-EZK 24-QFN Package Outline, 4 x 4 x 0.9 mm Body (Lead-Free) Table 9.1 24 Terminal QFN Package Parameters A A1 A2 D D1 D2 E E1 E2 L e b ccc MIN 0.70 0 ~ 3.85 3.55 2.40 3.85 3.55 2.40 0.30 0.18 ~ NOMINAL ~ 0.02 ~ 4.0 ~ 2.50 4.0 ~ 2.50 ~ 0.50 BSC 0.25 ~ MAX 1.00 0.05 0.90 4.15 3.95 2.60 4.15 3.95 2.60 0.50 0.30 0.
PAGE 77
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Figure 9.1 QFN, 4x4 Taping Dimensions and Part Orientation SMSC LAN8720/LAN8720i 77 DATASHEET Revision 1.
PAGE 78
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Figure 9.2 Reel Dimensions Note: Standard reel size is 4000 pieces per reel. Revision 1.
PAGE 79
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support Datasheet Chapter 10 Revision History Table 10.1 Customer Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY Rev. 1.0 (05-28-09) Rev. 1.0 (04-15-09) SMSC LAN8720/LAN8720i CORRECTION Revised LAN8720 ordering information. Initial Release 79 DATASHEET Revision 1.