- Standard Microsystems Ethernet Switch Specifications Sheet

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SMSC LAN9311/LAN9311i DATASHEET Revision 1.4 (08-19-08)

Datasheet

PRODUCT FEATURES

LAN9311/LAN9311i

Two Port 10/100 Managed

Ethernet Switch with 16-Bit

Non-PCI CPU Interface

Highlights

 High performance and full featured 2 port switch with

VLAN, QoS packet prioritization, Rate Limiting, IGMP

Snooping and management functions

 Easily interfaces to most 16-bit embedded CPU’s

 Unique Virtual PHY feature simplifies software

development by mimicking the multiple switch ports

as a single port MAC/PHY

 Integrated IEEE 1588 Hardware Time Stamp Unit

Target Applications

 Cable, satellite, and IP set-top boxes

 Digital televisions

 Digital video recorders

 VoIP/Video phone systems

 Home gateways

 Test/Measurement equipment

 Industrial automation systems

Key Benefits

 Ethernet Switch Fabric

— 32K buffer RAM

— 1K entry forwarding table

— Port based IEEE 802.1Q VLAN support (16 groups)

– Programmable IEEE 802.1Q tag insertion/removal

— IEEE 802.1d spanning tree protocol support

— QoS/CoS Packet prioritization

– 4 dynamic QoS queues per port

– Input priority determined by VLAN tag, DA lookup,

TOS, DIFFSERV or port default value

– Programmable class of service map based on input

priority

– Remapping of 802.1Q priority field on per port basis

– Programmable rate limiting at the ingress/egress

ports with random early discard, per port / priority

— IGMP v1/v2/v3 snooping for Multicast packet filtering

— IPV6 Multicast Listener Discovery snoop

— Programmable filter by MAC address

 Switch Management

— Port mirroring/monitoring/sniffing: ingress and/or egress

traffic on any ports or port pairs

— Fully compliant statistics (MIB) gathering counters

— Control registers configurable on-the-fly

 Ports

— 2 internal 10/100 PHYs with HP Auto-MDIX support

— Fully compliant with IEEE 802.3 standards

— 10BASE-T and 100BASE-TX support

— Full and half duplex support

— Full duplex flow control

— Backpressure (forced collision) half duplex flow control

— Automatic flow control based on programmable levels

— Automatic 32-bit CRC generation and checking

— Automatic payload padding

— 2K Jumbo packet support

— Programmable interframe gap, flow control pause value

— Full transmit/receive statistics

— Auto-negotiation

— Automatic MDI/MDI-X

— Loop-back mode

 High-performance host bus interface

— Provides in-band network communication path

— Access to management registers

— Simple, SRAM-like interface

— 16-bit data bus

— Big, little, and mixed endian support

— Large TX and RX FIFO’s for high latency applications

— Programmable water marks and threshold levels

— Host interrupt support

 IEEE 1588 Hardware Time Stamp Unit

— Global 64-bit tunable clock

— Master or slave mode per port

— Time stamp on TX or RX of Sync and Delay_req

packets per port, Timestamp on GPIO

— 64-bit timer comparator event generation (GPIO or IRQ)

 Comprehensive Power Management Features

— Wake on LAN

— Wake on link status change (energy detect)

— Magic packet wakeup

— Wakeup indicator event signal

 Other Features

— General Purpose Timer

— Serial EEPROM interface (I

C master or Microwire

master) for non-managed configuration

— Programmable GPIOs/LEDs

 Single 3.3V power supply

 Available in Commercial & Industrial Temp. Ranges

Summary of content (460 pages)

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LAN9311/LAN9311i Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface PRODUCT FEATURES Datasheet Highlights — — — — — — — — — — — — — — — High performance and full featured 2 port switch with VLAN, QoS packet prioritization, Rate Limiting, IGMP Snooping and management functions Easily interfaces to most 16-bit embedded CPU’s Unique Virtual PHY feature simplifies software development by mimicking the multiple switch ports as a single port MAC/PHY Integrated IEEE 1588 Ha
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet ORDER NUMBERS: LAN9311-NU FOR 128-PIN, VTQFP LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO 70°C TEMP RANGE) LAN9311-NZW FOR 128-PIN, XVTQFP LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO 70°C TEMP RANGE) LAN9311i-NZW FOR 128-PIN, XVTQFP LEAD-FREE ROHS COMPLIANT PACKAGE (-40 TO 85°C TEMP RANGE) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table of Contents Chapter 1 Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.1 1.2 1.3 General Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 5.2.7 5.2.8 5.2.9 General Purpose Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Device Ready Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2.1.6 100M Phase Lock Loop (PLL) ........................................................................................................................................................................ 86 7.2.2 100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.2.2.1 7.2.2.2 7.2.2.3 7.2.2.4 7.2.2.5 7.2.2.6 7.2.2.7 A/D Converter ...
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.6 HBI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Chapter 9 Host MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.1 9.2 9.2.1 9.2.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.5 9.5.1 9.6 9.7 9.7.1 9.7.2 9.7.3 9.8 9.8.1 9.8.2 Functional Overview . . . . . . . .
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.3.7 10.2.3.8 WRITE (Write Location) ................................................................................................................................................................................ 149 WRAL (Write All)...........................................................................................................................................................................................
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.3 GPIO/LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.2.3.1 14.2.3.2 14.2.3.3 14.2.3.4 General Purpose I/O Configuration Register (GPIO_CFG) ..........................................................................................................................
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.10 Host MAC VLAN2 Tag Register (HMAC_VLAN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.12 Host MAC Wake-up Control and Status Register (HMAC_WUCSR) . . . . . . . . . . . . . . . . . . . . . 14.4 Ethernet PHY Control and Status Registers. . . . . . . . . . . . . . . . . . . .
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.8 14.5.3.9 14.5.3.10 14.5.3.11 14.5.3.12 14.5.3.13 14.5.3.14 14.5.3.15 14.5.3.16 14.5.3.17 14.5.3.18 14.5.3.19 14.5.3.20 14.5.3.21 14.5.3.22 14.5.3.23 14.5.3.24 14.5.3.25 14.5.3.26 Switch Engine VLAN Command Register (SWE_VLAN_CMD).................................................................................................................... 377 Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA)..........
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.8 PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.9 TX Data FIFO Direct PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.10 Microwire Timing . . . . . . .
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet List of Figures Figure 2.1 Internal LAN9311/LAN9311i Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 2.2 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 3.1 LAN9311 128-VTQFP Pin Assignments (TOP VIEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Figure 14.1 LAN9311/LAN9311i Base Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15.2 nRST Reset Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet List of Tables Table 1.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 1.2 Register Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3.1 LAN Port 1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map . . . . . . . . . . . . Table 14.4 Virtual PHY MII Serially Adressable Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 14.5 Emulated Link Partner Pause Flow Control Ability Default Values . . . . . . . . . . . . . . . . . . . . Table 14.6 Host MAC Adressable Registers . . . . . . . . . . . . . . . . . . . . . . . . .
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 1 Preface 1.1 General Terms 100BT 100BASE-T (100Mbps Fast Ethernet, IEEE 802.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet MII Media Independent Interface MIIM Media Independent Interface Management MIL MAC Interface Layer MLD Multicast Listening Discovery MLT-3 Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 1.2 Buffer Types Table 1.1 describes the pin buffer type notation used in Chapter 3, "Pin Description and Configuration," on page 26 and throughout this document. Table 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 1.3 Register Nomenclature Table 1.2 describes the register bit attribute notation used throughout this document. Table 1.2 Register Bit Types REGISTER BIT TYPE NOTATION REGISTER BIT DESCRIPTION R Read: A register or bit with this attribute can be read. W Read: A register or bit with this attribute can be written. RO Read only: Read only. Writes have no effect.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 2 Introduction 2.1 General Description The LAN9311/LAN9311i is a full featured, 2 port 10/100 managed Ethernet switch designed for embedded applications where performance, flexibility, ease of integration and system cost control are required.
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Block Diagram IEEE 1588 Time Stamp Buffer Manager Frame Buffers 10/100 PHY MDIO Dynamic QoS 4 Queues MII To Ethernet Port 2 21 DATASHEET IEEE 1588 Time Stamp Search Engine 10/100 MAC IEEE 1588 Time Stamp Switch Registers (CSRs) Registers IEEE 1588 Time Stamp Clock/Events GPIO/LED Controller System Interrupt Controller System Clocks/ Reset/PME Controller GP Timer SMSC LAN9311/LAN9311i IRQ MDIO Host Bus Interface To 16-bit Host Bus EEPROM Loader EEPROM Controller I2C/Microwire 2 F
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 2.2.1 System Clocks/Reset/PME Controller A clock module contained within the LAN9311/LAN9311i generates all the system clocks required by the device. This module interfaces directly with the external 25MHz crystal/oscillator to generate the required clock divisions for each internal module, with the exception of the 1588 clocks, which are generated in the 1588 Time Stamp Clock/Events module.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet General Purpose Timer Software (general purpose) A dedicated programmable IRQ interrupt output pin is provided for external indication of any LAN9311/LAN9311i interrupts. The IRQ pin is controlled via the Interrupt Configuration Register (IRQ_CFG), which allows configuration of the IRQ buffer type, polarity, and de-assertion interval. 2.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 2.2.6 System CSRs Access Interrupt Support Host MAC The Host MAC incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3compliant node and provides an interface between the Host Bus Interface (HBI) and the Ethernet PHYs and Switch Fabric. On the front end, the Host MAC interfaces to the HBI via 2 sets of FIFO’s (TX Data FIFO, TX Status FIFO, RX Data FIFO, RX Status FIFO).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 2.2.9 GPIO/LED Controller The LAN9311/LAN9311i provides 12 configurable general-purpose input/output pins which are controlled via this module. These pins can be individually configured via the GPIO/LED CSRs to function as inputs, push-pull outputs, or open drain outputs and each is capable of interrupt generation with configurable polarity.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 3 Pin Description and Configuration VSS 97 EEDO/EEPROM_TYPE 98 EECLK/EE_SCL/ EEPROM_SIZE_1 99 NC NC VDD33IO nP1LED0/GPIO0 nP1LED1/GPIO1 nP1LED2/GPIO2 nP1LED3/GPIO3 VDD18CORE VDD33IO nP2LED0/GPIO4 nP2LED1/GPIO5 nP2LED2/GPIO6 nP2LED3/GPIO7 GPIO8 VDD33IO VSS GPIO9 GPIO10 GPIO11 NC TEST1 VDD18CORE VDD33IO VDD33IO nRST AUTO_MDIX_2 AUTO_MDIX_1 PHY_ADDR_SEL LED_EN VDD33IO VDD18CORE 94
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet VSS 97 EEDO/EEPROM_TYPE 98 EECLK/EE_SCL/ EEPROM_SIZE_1 99 EEDI/EE_SDA NC NC VDD33IO nP1LED0/GPIO0 nP1LED1/GPIO1 nP1LED2/GPIO2 nP1LED3/GPIO3 VDD18CORE VDD33IO nP2LED0/GPIO4 nP2LED1/GPIO5 nP2LED2/GPIO6 nP2LED3/GPIO7 GPIO8 VDD33IO VSS GPIO9 GPIO10 GPIO11 NC TEST1 VDD18CORE VDD33IO VDD33IO nRST AUTO_MDIX_2 AUTO_MDIX_1 PHY_ADDR_SEL LED_EN VDD33IO VDD18CORE 95 94 93 92 91 90 89 88 87
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 3.2 Pin Descriptions This section contains the descriptions of the LAN9311/LAN9311i pins.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Note 3.1 The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will be swapped internally. Table 3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 3.3 LAN Port 1 & 2 Power and Common Pins (continued) PIN NAME SYMBOL BUFFER TYPE VDD33A2 P 122,125 +3.3V Port 2 Analog Power Supply VDD33BIAS 120 +3.3V Master Bias Power Supply VDD18TX2 121 Port 2 Transmitter +1.8V Power Supply DESCRIPTION +3.3V Port 2 Analog Power Supply Refer to the LAN9311/LAN9311i application note for additional connection information. P +3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 3.4 Host Bus Interface Pins (continued) PIN NAME SYMBOL BUFFER TYPE Data FIFO Direct Access Select FIFO_SEL IS Data FIFO Direct Access Select: When driven high, all accesses to the LAN9311/LAN9311i are directed to the RX and TX Data FIFO’s. All reads are from the RX Data FIFO, and all writes are to the TX Data FIFO. In this mode, the address input is ignored. Refer to Section 14.1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 3.5 EEPROM Pins (continued) PIN NAME SYMBOL BUFFER TYPE EEPROM Microwire Chip Select EECS O8 DESCRIPTION EEPROM Microwire Chip Select: In Microwire EEPROM mode (EEPROM_TYPE = 0), this pin is the Microwire EEPROM chip select output. Note: 101 EEPROM Size Strap 0 EEPROM_SIZE_0 IS Note 3.3 In I2C mode (EEPROM_TYPE=1), this pin is not used and is driven low.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 3.6 Dedicated Configuration Strap Pins (continued) PIN 69 NAME SYMBOL Port 1 AutoMDIX Enable Strap AUTO_MDIX_1 BUFFER TYPE IS (PU) DESCRIPTION Port 1 Auto-MDIX Enable Strap: Configures the Auto-MDIX functionality on Port 1. When latched low, Auto-MDIX is disabled. When latched high, Auto-MDIX is enabled. See Note 3.6.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 3.7 Miscellaneous Pins (continued) PIN NAME SYMBOL BUFFER TYPE Test 1 TEST1 AI Test 1: This pin must be tied to VDD33IO for proper operation. Test 2 TEST2 AI Test 2: This pin must be tied to VDD33IO for proper operation. Power Management Event PME O8/OD8 75 108 62 DESCRIPTION Power Management Event: When programmed accordingly, this signal is asserted upon detection of a wakeup event.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 3.9 Core and I/O Power and Ground Pins (continued) PIN NAME SYMBOL BUFFER TYPE 18,48,80, 97,112,113, 128 Common Ground VSS P DESCRIPTION Common Ground Note 3.8 Note 3.8 Plus external pad for 128-XVTQFP package only Table 3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 4 Clocking, Resets, and Power Management 4.1 Clocks The LAN9311/LAN9311i includes a clock module which provides generation of all system clocks as required by the various sub-modules of the device. The LAN9311/LAN9311i requires a fixed-frequency 25MHz clock source for use by the internal clock oscillator and PLL.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SYSTEM CLOCKS/RESET/PME SYS INTERRUPTS SWITCH FABRIC ETHERNET PHYS HBI HOST MAC EEPROM CONTROLLER 1588 TIME STAMP GPIO/LED CONTROLLER CONFIG. STRAPS LATCHED EEPROM LOADER RUN Table 4.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet A POR reset typically takes approximately 23mS, plus additional time (91uS for I2C, 28uS for Microwire) per byte of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load (64KB for I2C, 2KB for Microwire) will complete in approximately 6.0 seconds for I2C EEPROM, and 80mS for Microwire EEPROM. 4.2.1.2 nRST Pin Reset Driving the nRST input pin low initiates a chip-level reset.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 4.2.2.2 Soft Reset (SRST) A soft reset is performed by setting the SRST bit of the Hardware Configuration Register (HW_CFG). A soft reset will reset the HBI, Host MAC, and System CSRs below address 100h. The soft reset also clears any TX or RX errors in the Host MAC transmitter and receiver (TXE/RXE). This reset does not latch the configuration straps.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Note: When using the Reset bit to reset the Port 1 PHY, register bits designated as NASR are not reset. Refer to Section 7.2.10, "PHY Resets," on page 95 for additional information on Port 1 PHY resets. 4.2.3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions PIN / DEFAULT VALUE STRAP NAME DESCRIPTION LED_en_strap[7:0] LED Enable Straps: Configures the default value for the LED_EN bits in the LED Configuration Register (LED_CFG). A high value configures the associated LED/GPIO pin as a LED. A low value configures the associated LED/GPIO pin as a GPIO.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions (continued) PIN / DEFAULT VALUE STRAP NAME DESCRIPTION speed_strap_1 Port 1 Speed Select Strap: Configures the default value for the Speed Select LSB (PHY_SPEED_SEL_LSB) bit in the PHY_BASIC_CTRL_1 register (See Section 14.4.2.1). When configured low, 10 Mbps is selected. When configured high, 100 Mbps is selected.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions (continued) PIN / DEFAULT VALUE STRAP NAME DESCRIPTION manual_FC_strap_1 Port 1 Manual Flow Control Enable Strap: Configures the default value of the Port 1 Full-Duplex Manual Flow Control Select (MANUAL_FC_1) bit in the Port 1 Manual Flow Control Register (MANUAL_FC_1).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions (continued) PIN / DEFAULT VALUE STRAP NAME DESCRIPTION speed_strap_2 Port 2 Speed Select Strap: Configures the default value for the Speed Select LSB (PHY_SPEED_SEL_LSB) bit in the PHY_BASIC_CTRL_2 register (See Section 14.4.2.1). When configured low, 10 Mbps is selected. When configured high, 100 Mbps is selected.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions (continued) PIN / DEFAULT VALUE STRAP NAME DESCRIPTION manual_FC_strap_2 Port 2 Manual Flow Control Enable Strap: Configures the default value of the Port 2 Full-Duplex Manual Flow Control Select (MANUAL_FC_2) bit in the Port 2 Manual Flow Control Register (MANUAL_FC_2).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 4.3 Hard-Strap Configuration Strap Definitions STRAP NAME eeprom_type_strap DESCRIPTION EEPROM Type Strap: Configures the EEPROM type. PIN EEPROM_TYPE 0 = Microwire Mode 1 = I2C Mode PHY Address Select Strap: Configures the default MII management address values for the PHYs and Virtual PHY as detailed in Section 7.1.1, "PHY Addressing," on page 82. PHY_ADDR_SEL 4.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet WUFR (bit 6) of HMAC_WUCSR register WOL_EN (bit 9) of PMT_CTRL register Host MAC WUEN (bit 2) of HMAC_WUCSR register WOL_STS (bit 5) of PMT_CTRL register MPR (bit 5) of HMAC_WUCSR register MPEN (bit 1) of HMAC_WUCSR register ED_EN1 (bit 14) of PMT_CTRL register Port 1 & 2 PHYs INT7 (bit 7) of PHY_INTERRUPT_SOURCE_1 register ED_STS1 (bit 16) of PMT_CTRL register INT7_MASK (bit 7) of PHY_INTERRUPT_SOURCE_1 register
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet The Port 1 & 2 PHY energy-detect events are capable of asserting the PME output by additionally setting the PME_EN and ED_EN2 (Port 2 PHY) or ED_EN1 (Port 1 PHY) bits of the Power Management Control Register (PMT_CTRL). 4.3.2 Host MAC Power Management The Host MAC provides wake-up frame and magic packet detection modes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 5 System Interrupts 5.1 Functional Overview This chapter describes the system interrupt structure of the LAN9311/LAN9311i. The LAN9311/LAN9311i provides a multi-tier programmable interrupt structure which is controlled by the System Interrupt Controller.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Top Level Interrupt Registers (System CSRs) INT_CFG INT_STS INT_EN Bit 29 (1588_EVNT) of INT_STS register 1588 Time Stamp Interrupt Register 1588_INT_STS_EN Switch Fabric Interrupt Registers Bit 28 (SWITCH_INT) of INT_STS register SW_IMR SW_IPR Buffer Manager Interrupt Registers Bit 6 (BM) of SW_IPR register BM_IMR BM_IPR Switch Engine Interrupt Registers Bit 5 (SWE) of SW_IPR register SWE_IMR SWE_IPR Port [2,1,0]
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet The following sections detail each category of interrupts and their related registers. Refer to Chapter 14, "Register Descriptions," on page 167 for bit-level definitions of all interrupt registers. 5.2.1 1588 Time Stamp Interrupts Multiple 1588 Time Stamp interrupt sources are provided by the LAN9311/LAN9311i.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 5.2.3 Ethernet PHY Interrupts The Port 1 and Port 2 PHYs each provide a set of identical interrupt sources. The top-level PHY_INT1 (bit 26) and PHY_INT2 (bit 27) of the Interrupt Status Register (INT_STS) provides indication that a PHY interrupt event occurred in the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet TX Status FIFO Overflow Receive Watchdog Time-Out Receiver Error Transmitter Error TX Data FIFO Underrun TX Data FIFO Overrun TX Data FIFO Available TX Status FIFO Full TX Status FIFO Level RX Dropped Frame RX Data FIFO Level RX Status FIFO Full RX Status FIFO Level In order for a Host MAC interrupt event to trigger the external IRQ interrupt pin, the desired Host MAC inte
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 5.2.8 Software Interrupt A general purpose software interrupt is provided in the top level Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN). The SW_INT interrupt (bit 31) of the Interrupt Status Register (INT_STS) is generated when SW_INT_EN (bit 31) of the Interrupt Enable Register (INT_EN) is set.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 6 Switch Fabric 6.1 Functional Overview At the core of the LAN9311/LAN9311i is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.2.1 Switch Fabric CSR Writes To perform a write to an individual switch fabric register, the desired data must first be written into the Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet CSR Write CSR Write Auto Increment / Decrement Idle Idle Idle Write Data Register Write Command Register Write Direct Data Register Range CSR Write Direct Address min wait period Write Command Register Write Data Register CSR_BUSY = 0 Read Command Register CSR_BUSY = 1 min wait period CSR_BUSY = 0 Read Command Register min wait period CSR_BUSY = 0 CSR_BUSY = 1 Read Command Register CSR_BUSY = 1 Figure 6
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet CSR Read CSR Read Auto Increment / Decrement Idle Idle Write Command Register Write Command Register min wait period min wait period min wait period CSR_BUSY = 1 CSR_BUSY = 1 Read Command Register Read Command Register CSR_BUSY = 0 CSR_BUSY = 0 last data? Read Data Register No Read Data Register Yes Write Command Register Read Data Register Figure 6.2 Switch Fabric CSR Read Access Flow Diagram 6.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet register. When Auto-negotiation is enabled and the MANUAL_FC_x bit is cleared, the switch port flow control enables during full-duplex are determined by Auto-negotiation. Note: The flow control values in the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_AD V_ x) an d Virtual PHY Au to -N egotia tio n Advertisement Register (VPHY_AN_ADV) are not affected by the values of the manual flow control register.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Per Table 6.1, the following cases are possible: Case 1 - Auto-negotiation is still in progress. Since the result is not yet established, flow control is disabled. Case 2 - Auto-negotiation is enabled and unsuccessful (link partner not Auto-negotiation capable). The link partner ability is undefined, effectively a don’t-care value, in this case. The duplex setting will default to half-duplex in this case.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet "Flow Control Enable Logic," on page 58. Pause frames are consumed by the MAC and not sent to the switch engine. Non-pause control frames are optionally filtered or forwarded. When the receive FIFO is full and additional data continues to be received, an overrun condition occurs and the frame is discarded (FIFO space recovered) or marked as a bad frame.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.3.2 Transmit MAC The transmit MAC generates an Ethernet MAC frame from TX FIFO data. This includes generating the preamble and SFD, calculating and appending the frame checksum value, optionally padding undersize packets to meet the minimum packet requirement size (64 bytes), and maintaining a standard inter-frame gap time during transmit.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.4 Total multicast packets (Section 14.5.2.37, on page 360) Total packets with a late collision (Section 14.5.2.38, on page 361) Total packets with excessive collisions (Section 14.5.2.39, on page 362) Total packets with a single collision (Section 14.5.2.40, on page 363) Total packets with multiple collisions (Section 14.5.2.41, on page 364) Total collision count (Section 14.5.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.4.1.1 Learning/Aging/Migration The ALR adds new MAC addresses upon ingress along with the associated receive port. If the source MAC address already exists, the entry is refreshed. This action serves two purposes. First, if the source port has changed due to a network reconfiguration (migration), it is updated. Second, each instance the entry is refreshed, the aging status bit is set, keeping the entry active.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet The following procedure should be followed in order to add, delete, and modify the ALR entries: 1. Write the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) with the desired MAC address and control bits. Note:An entry can be deleted by setting the Valid and Static bits to 0. 2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.4.2 Forwarding Rules Upon ingress, packets are filtered or forwarded based on the following rules: If the destination port equals the source port (local traffic), the packet is filtered. If the source port is not in the forwarding state, the packet is filtered (unless the Spanning Tree Port State Override is in effect).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.4.3 Transmit Priority Queue Selection The transmit priority queue may be selected from five options. As shown in Figure 6.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet The transmit queue priority is based on the packet type and device configuration as shown in Figure 6.5 . Refer to Section 14.5.3.16, "Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)," on page 385 for definitions of the configuration bits.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.4.3.1 Port Default Priority As detailed in Figure 6.5, the default priority is based on the ingress ports priority bits in its port VID value.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.4.4 VLAN Support The switch engine supports 16 active VLANs out of a possible 4096. The VLAN table contains the 16 active VLAN entries, each consisting of the VID, the port membership, and un-tagging instructions. 17 16 15 14 13 12 Member Port 2 Un-tag Port 2 Member Port 1 Un-tag Port 1 Member MII Un-tag MII 11 ... 0 VID Figure 6.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 6.2 Spanning Tree States (continued) Port State 11 - Listening Hardware Action Software Action Received packets on the port are discarded. Transmissions to the port are blocked. 10 - Learning Learning on the port is disabled. The host CPU may send packets to the port in this state. Received packets on the port are discarded.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 6.3 Typical Ingress Rate Settings CIR Setting Time Per Byte Bandwidth 0-3 80 nS 100 Mbps 4 100 nS 80 Mbps 5 120 nS 67 Mbps 6 140 nS 57 Mbps 7 160 nS 50 Mbps 9 200 nS 40 Mbps 12 260 nS 31 Mbps 19 400 nS 20 Mbps 39 800 nS 10 Mbps 79 1600 nS 5 Mbps 160 3220 nS 2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Packet is from Host Packet is Tagged Packet is IPv 4 Packet is IP VL Higher Priority Use Precedence Use IP VLAN Enable 6b IPv4(TOS) IPv6(TC) Programmable DIFFSERV Table 3b 3b IPv4 Precedence flow priority Programmable Port Default Table 2b Source Port 3b Priority Calculation 3b 3b VLAN Priority Figure 6.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.4.7 Broadcast Storm Control In addition to ingress rate limiting, the LAN9311/LAN9311i supports hardware broadcast storm control on a per port basis. This feature is enabled via the Switch Engine Broadcast Throttling Register (SWE_BCST_THROT). The allowed rate per port is specified as the number of bytes multiplied by 64 allowed to be received every 1.72 mS interval. Packets that exceed this limit are dropped.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Normally, packets are never transmitted back to the receiving port. For IGMP/MLD snooping, this may optionally be enabled via the Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG). This function would be used if the snooping port wished to participate in the IGMP/MLD group without the need to perform special handling in the transmit portion of the driver software.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Note: When specifying Port 0 as the destination port, the VID will be set to 0. A VID of 0 is normally considered a priority tagged packet. Such a packet will be filtered if Admit Only VLAN is set on the host CPU port. Either avoid setting Admit Only VLAN on the host CPU port or set an unused bit in the VID field.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.5 Buffer Manager (BM) The buffer manager (BM) provides control of the free buffer space, the multiple priority transmit queues, transmission scheduling, and packet dropping. VLAN tag insertion and removal is also performed by the buffer manager. The following sections detail the various features of the buffer manager. 6.5.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.5.4 Transmit Priority Queue Servicing When a transmit queue is non-empty, it is serviced and the packet is read from the buffer RAM and sent to the transmit MAC. If there are multiple queues that require servicing, one of two methods may be used: fixed priority ordering, or weighted round-robin ordering.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.5.6 Adding, Removing, and Changing VLAN Tags Based on the port configuration and the received packet formation, a VLAN tag can be added to, removed from, or modified in a packet. There are four received packet type cases: non-tagged, prioritytagged, normal-tagged, and CPU special-tagged. There are also four possible settings for an egress port: dumb, access, hybrid, and CPU.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Hybrid tagging is summarized in Figure 6.9.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.5.7 Counters A counter is maintained per port that contains the number of packets dropped due to buffer space limits and ingress rate limit discarding (Red and random Yellow dropping).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 7 Ethernet PHYs 7.1 Functional Overview The LAN9311/LAN9311i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2 Port 1 & 2 PHYs Functionally, each PHY can be divided into the following sections: 100BASE-TX Transmit and 100BASE-TX Receive 10BASE-T Transmit and 10BASE-T Receive PHY Auto-negotiation HP Auto-MDIX MII MAC Interface PHY Management Control Note 7.1 Because the Port 1 PHY and Port 2 PHY are functionally identical, this section will describe them as the “Port x PHY”, or simply “PHY”.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2.1 100BASE-TX Transmit The 100BASE-TX transmit data path is shown in Figure 7.2. Shaded blocks are those which are internal to the PHY. Each major block is explained in the following sections.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 7.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 7.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2.2 100BASE-TX Receive The 100BASE-TX receive data path is shown in Figure 7.3. Shaded blocks are those which are internal to the PHY. Each major block is explained in the following sections.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2.2.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. 7.2.2.4 Descrambler and SIPO The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. During reception of IDLE (/I/) symbols.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2.3 10BASE-T Transmit Data to be transmitted comes from the switch fabric MAC. The 10BASE-T transmitter receives 4-bit nibbles from the internal MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. 10BASE-T transmissions use the following blocks: 7.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet (PHY_SPECIAL_CONTROL_STAT_IND_x). The 10M PLL locks onto the received Manchester signal and generates the received 20MHz clock from it. Using this clock, the Manchester encoded data is extracted and converted to a 10MHz NRZI data stream. It is then converted from serial to 4-bit wide parallel data. The RX10M block also detects valid 10BASE-T IDLE signals - Normal Link Pulses (NLPs) - to maintain the link. 7.2.4.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10M PLL (analog) 10M TX Driver (analog) Auto-negotiation is started by the occurrence of any of the following events: Power-On Reset (POR) Hardware reset (nRST) PHY Software reset (via Reset Control Register (RESET_CTL), or bit 15 of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)) PHY Power-down reset (Section 7.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2.5.1 PHY Pause Flow Control The Port 1 & 2 PHYs are capable of generating and receiving pause flow control frames per the IEEE 802.3 specification. The PHYs advertised pause flow control abilities are set via bits 10 (Symmetric Pause) and 11 (Asymmetric Pause) of the Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2.5.5 Half Vs. Full-Duplex Half-duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity. If data is received while the PHY is transmitting, a collision results. In full-duplex mode, the PHY is able to transmit and receive data simultaneously.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet For a transmission, the switch fabric MAC drives the transmit data onto the internal MII TXD bus and asserts TXEN to indicate valid data. The data is in the form of 4-bit wide data at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T. For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are clocked to the controller at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Note: The power-down modes of each PHY (Port 1 PHY and Port 2 PHY) are controlled independently. Note: The PHY power-down modes do not reload or reset the PHY registers. 7.2.9.1 PHY General Power-Down This power-down mode is controlled by bit 11 of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). In this mode the entire PHY, except the PHY management control interface, is powered down.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2.10.2 PHY Software Reset via PHY_BASIC_CTRL_x The PHY can also be reset by setting bit 15 (PHY_RST) of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). This bit is self clearing and will return to 0 after the reset is complete. This reset does not reload the configuration strap values into the PHY registers. 7.2.10.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet The emulated auto-negotiation process is much simpler than the real process and can be categorized into three steps: 1. Bit 5 (Auto-Negotiation Complete) is set in the Virtual PHY Basic Status Register (VPHY_BASIC_STATUS). 2. Bit 1 (Page Received) is set in the Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP). 3. The auto-negotiation result (speed and duplex) is determined and registered.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet (VPHY_BASIC_CTRL). The speed and duplex bits in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) should be ignored when auto-negotiation is enabled. 7.3.1.3 Virtual PHY Pause Flow Control The Virtual PHY supports pause flow control per the IEEE 802.3 specification.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 8 Host Bus Interface (HBI) 8.1 Functional Overview The Host Bus Interface (HBI) module provides a high-speed asynchronous SRAM-like slave interface that facilitates communication between the LAN9311/LAN9311i and a host system. The HBI allows access to the System CSRs and handles byte swapping based on the dynamic endianess select.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.3.1 16-Bit Bus Writes The host is required to perform two contiguous 16-bit writes to complete a single DWORD transfer. The DWORD must not cross a DWORD address boundary (A[2] and higher cannot change between a pair of writes). No ordering requirements exist. The host can access either the low or high word first, as long as the next write is performed on the other word.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet . 16-BIT LITTLE ENDIAN (END_SEL = 0) INTERNAL ORDER MSB 31 LSB 24 23 3 16 15 8 2 1 A[1] = 1 3 2 A[1] = 0 1 0 15 8 7 7 0 0 0 HOST DATA BUS Figure 8.1 Little Endian Byte Ordering . 16-BIT BIG ENDIAN (END_SEL = 1) INTERNAL ORDER MSB 31 LSB 24 23 3 16 15 8 2 1 A[1] = 1 0 1 A[1] = 0 2 3 15 8 7 7 0 0 0 HOST DATA BUS Figure 8.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.5 Host Interface Timing This section details the characteristics and special restrictions of the various supported host cycles. For detailed timing specifications on supported PIO read/write operations, refer to Section 15.5, "AC Specifications".
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 8.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 8.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 8.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.5.3 Special Restrictions on Back-to-Back Read Cycles There are also restrictions on specific back-to-back host read operations. These restrictions concern reading specific registers after reading a resource that has side effects. In many cases there is a delay between reading the LAN9311/LAN9311i, and the subsequent indication of the expected change in the control and status register values.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.5.4 PIO Reads PIO reads can be used to access System CSR’s or RX Data and RX/TX Status FIFOs. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Read cycle begins when both nCS and nRD are asserted. Either or both of these control signals must de-assert between cycles for the period specified in Table 15.8, “PIO Read Cycle Timing Values,” on page 448.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.5.5 PIO Burst Reads In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO burst reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Burst Read begins when both nCS and nRD are asserted. Either or both of these control signals must de-assert between bursts for the period specified in Table 15.9, “PIO Burst Read Cycle Timing Values,” on page 449.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.5.6 RX Data FIFO Direct PIO Reads In this mode only A[2:1] are decoded, and any read of the LAN9311/LAN9311i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9311/LAN9311i.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.5.7 RX Data FIFO Direct PIO Burst Reads In this mode only A[2:1] are decoded, and any burst read of the LAN9311/LAN9311i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9311/LAN9311i.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.5.8 PIO Writes PIO writes are used for all LAN9311/LAN9311i write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are de-asserted. Either or both of these control signals must de-assert between cycles for the period specified in Table 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.5.9 TX Data FIFO Direct PIO Writes In this mode only A[2:1] are decoded, and any write to the LAN9311/LAN9311i will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9311/LAN9311i.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 9 Host MAC 9.1 Functional Overview The Host MAC incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3compliant node and provides an interface between the Host Bus Interface (HBI) and the Ethernet PHYs and Switch Fabric. On the front end, the Host MAC interfaces to the HBI via 2 sets of FIFO’s (TX Data FIFO, TX Status FIFO, RX Data FIFO, RX Status FIFO).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.2 Flow Control The Host MAC supports full-duplex flow control using the pause operation and control frame. Halfduplex flow control using back pressure is also supported. The Host MAC flow control is configured via the memory mapped Host MAC Automatic Flow Control Configuration Register (AFC_CFG) located in the System CSR space and the Host MAC Flow Control Register (HMAC_FLOW) located in the Host MAC CSR space.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet should be unique. If both are set to the same value, VLAN1 is given higher precedence and the maximum legal frame length is set to 1522. Standard Ethernet Frame (1518 Bytes) Preamble 7 Bytes SOF 1 Byte Dest. Addr. 6 Bytes Source Addr. 6 Bytes Type 2 Bytes Data 46-1500 Bytes FCS 4 Bytes Ethernet Frame with VLAN TAG (1522 Bytes) Preamble 7 Bytes SOF 1 Byte Dest. Addr. 6 Bytes Source Addr.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 9.1 Address Filtering Modes MCPAS PRMS INVFILT HO HPFILT DESCRIPTION 0 0 0 0 0 MAC address perfect filtering only for all addresses.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.4.4 Inverse Filtering In inverse filtering, the Host MAC packet filter accepts incoming frames (from switch Port 0) with a destination address not matching the perfect address (i.e., the value programmed into the Host MAC Address High Register (HMAC_ADDRH) and the Host MAC Address Low Register (HMAC_ADDRL)) and rejects frames with destination addresses matching the perfect address.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 9.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet The Filter i Offset register defines the offset in the frame’s destination address field from which the frames are examined by Filter i. Table 9.5 describes the Filter i Offset bit fields. Table 9.5 Filter i Offset Bit Definitions FILTER i OFFSET DESCRIPTION FIELD 7:0 DESCRIPTION Pattern Offset: The offset of the first byte in the frame on which CRC is checked for wake-up frame recognition.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Destination Address Source Address ……………FF FF FF FF FF FF 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 …CRC Note: The switch fabric must be configured to pass magic packets to the Hos
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 31 24 23 xx 16 15 xx 8 7 BCh 0 9Ah HMAC_ADDRH / SWITCH_MAC_ADDRH 31 24 23 78h 16 15 56h 8 7 34h 0 12h HMAC_ADDRL / SWITCH_MAC_ADDRL 06h BCh 05h 9Ah 04h 78h 03h 56h 02h 34h 01h 12h 00h A5h EEPROM Figure 9.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet operations, the MIL operates in store-and-forward mode and will queue an entire frame before beginning transmission. As space in the TX MIL FIFO frees, data is moved into it from the TX Data FIFO. Depending on the size of the frames to be transmitted, the Host MAC can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX Data FIFO.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 9.9 Valid TX/RX FIFO Allocations 9.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet The LAN9311/LAN9311i can be programmed to strip padding from the end of a transmit packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9311/LAN9311i is operating in a system that always performs multi-word bursts.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.8.1 TX Buffer Format TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32bit values that are used by the LAN9311/LAN9311i in the handling and processing of the associated Ethernet packet data buffer.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do not match, the Ethernet controller will assert the Transmitter Error (TXE) flag. 9.8.2.1 TX Command ‘A’ Table 9.10 TX Command 'A' Format BITS 31 DESCRIPTION Interrupt on Completion (IOC).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.8.2.2 TX Command ‘B’ Table 9.11 TX Command 'B' Format BITS DESCRIPTION 31:16 Packet Tag. The host should write a unique packet identifier to this field. This identifier is added to the corresponding TX status word and can be used by the host to correlate TX status words with their corresponding packets. Note: 15:14 The use of packet tags is not required by the hardware.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to the LAN9311/LAN9311i. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION 8 Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16 collisions while attempting to transmit the current packet. 7 Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility. 6:3 Collision Count. This counter indicates the number of collisions that occurred before the packet was transmitted.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Figure 9.5 illustrates the TX command structure for this example, and also shows how data is passed to the TX Data FIFO.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.8.6.2 TX Example 2 In this example, a single 183-Byte Ethernet packet will be transmitted. This packet is in a single buffer as follows: 2-Byte “Data Start Offset” 183-Bytes of payload data 4-Byte “Buffer End Alignment” Figure 9.6 illustrates the TX command structure for this example, and also shows how data is passed to the TX Data FIFO.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.8.7 Transmitter Errors If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation. TX Error (TXE) will be asserted under the following conditions: 9.8.8 If the actual packet length count does not match the Packet Length field as defined in the TX command. Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.9 RX Data Path Operation When an Ethernet Packet is received, the Host MAC Interface Layer (MIL) first begins to transfer the RX data. This data is loaded into the RX Data FIFO. The RX Data FIFO pointers are updated as data is written into the FIFO. The last transfer from the MIL is the RX status word. The LAN9311/LAN9311i implements a separate FIFO for the RX status words.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet init Idle RX Interrupt Read RX Status DWORD Not Last Packet Last Packet Read RX Packet Figure 9.7 Host Receive Routine Using Interrupts init Read RX_FIFO_INF Valid Status DWORD Read RX Status DWORD Not Last Packet Last Packet Read RX Packet Figure 9.8 Host Receive Routine Using Polling Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.9.1.1 Receive Data FIFO Fast Forward The RX data path implements an automatic data discard function. Using the RX Data FIFO Fast Forward bit (RX_FFWD) in the Receive Datapath Control Register (RX_DP_CTRL), the host can instruct the LAN9311/LAN9311i to skip the packet at the head of the RX Data FIFO. The RX Data FIFO pointers are automatically incremented to the beginning of the next RX packet.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.9.3 RX Status Format Note: Though the Host MAC is communicating locally with the switch fabric MAC, the events described in the RX Status word may still occur. BITS DESCRIPTION 31 Reserved. This bit is reserved. Reads 0. 30 Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing filtering. 29:16 Packet Length. The size, in bytes, of the corresponding received frame.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.9.4 Stopping and Starting the Receiver To stop the receiver, the host must clear the RXEN bit in the Host MAC Control Register (HMAC_CR). When the receiver is halted, the RXSTOP_INT will be pulsed and reflected in the Interrupt Status Register (INT_STS). Once stopped, the host can optionally clear the RX Status and RX Data FIFOs. The host must re-enable the receiver by setting the RXEN bit. 9.9.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 10 Serial Management 10.1 Functional Overview This chapter details the LAN9311/LAN9311i serial management functionality of the I 2C/Microwire EEPROM Controller and the supporting EEPROM Loader. The I2C/Microwire EEPROM controller is an I2C/Microwire master module which interfaces an optional external EEPROM with the system register bus and the EEPROM Loader.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.1 EEPROM Controller Operation I2C and Microwire master EEPROM operations are performed using the EEPROM Command Register (E2P_CMD) and EEPROM Data Register (E2P_DATA).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Figure 10.1 illustrates the process required to perform an EEPROM read or write operation. EEPROM Write EEPROM Read Idle Idle Write E2P_DATA Register Write E2P_CMD Register Write E2P_CMD Register Read E2P_CMD Register EPC_BUSY = 0 EPC_BUSY = 0 Read E2P_CMD Register Read E2P_DATA Register Figure 10.1 EEPROM Access Flow Diagram 10.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet controller drives all the address bits as requested regardless of the actual size of the EEPROM. The supported size ranges for I2C operation are shown in Table 10.2. Table 10.2 I2C EEPROM Size Ranges eeprom_size_strap[0] # OF ADDRESS BYTES EEPROM SIZE EEPROM TYPES 0 1 (Note 10.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Figure 10.2 displays the various bus states of a typical I2C cycle. data can change data stable data can change data can change data can change data stable EE_SDA S Sr P EE_SCL Start Condition Data Valid or Ack Data Valid or Ack Re-Start Condition Stop Condition Figure 10.2 I2C Cycle I2C EEPROM Device Addressing 10.2.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.2.3 I2C EEPROM Byte Read Following the device addressing, a data byte may be read from the EEPROM by outputting a start condition and control byte with a control code of 1010b, chip/block select bits as described in Section 10.2.2.2, and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by 8-bits of data.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Sequential reads are used by the EEPROM Loader. Refer to Section 10.2.4, "EEPROM Loader" for additional information. For a register level description of a read operation, refer to Section 10.2.1, "EEPROM Controller Operation," on page 139. 10.2.2.5 I2C EEPROM Byte Writes Following the device addressing, a data byte may be written to the EEPROM by outputting the data after receiving the acknowledge from the EEPROM.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.3 Microwire EEPROM Based on the configuration strap eeprom_type_strap, various sized Microwire EEPROMs are supported. The varying size ranges are supported by additional bits in the address field (EPC_ADDRESS) of the EEPROM Command Register (E2P_CMD). Within each size range, the largest EEPROM uses all the address bits, while the smaller EEPROMs treat the upper address bits as don’t cares.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 10.5 Microwire Command Set for 9 Address Bits (continued) INST START BIT OPCODE ADDRESS DATA TO EEPROM DATA FROM EEPROM # OF CLOCKS EWDS 1 00 0 0 X X X X X X X - Hi-Z 12 EWEN 1 00 1 1 X X X X X X X - Hi-Z 12 READ 1 10 A8 A7 A6 A5 A4 A3 A2 A1 A0 - D7 - D0 20 WRITE 1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/~BSY) 20 WRAL 1 00 0 1 X X X X X X X D7 - D0 (RDY/~BSY) 20 Table 10.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.3.3 ERAL (Erase All) If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM. The EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) is set if the EEPROM does not respond within 30mS. EECS EECLK EEDO 1 0 0 1 0 EEDI Figure 10.8 EEPROM ERAL Cycle 10.2.3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.3.5 EWEN (Erase/Write Enable) This command enables the EEPROM for erase and write operations. The EEPROM will allow erase and write operations until the EWDS command is sent, or until power is cycled. Note: The EEPROM will power-up in the erase/write disabled state. Any erase or write operations will fail until an EWEN command is issued. EECS EECLK EEDO 1 0 0 1 1 EEDI Figure 10.10 EEPROM EWEN Cycle 10.2.3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.3.7 WRITE (Write Location) If erase/write operations are enabled in the EEPROM, this command will cause the contents of the EEPROM Data Register (E2P_DATA) to be written to the EEPROM location pointed to by the EPC_ADDRESS field of the EEPROM Command Register (E2P_CMD). The EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) is set if the EEPROM does not respond within 30mS.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.4 EEPROM Loader The EEPROM Loader interfaces to the I2C/Microwire EEPROM controller, the PHYs, and to the system CSRs (via the Register Access MUX). Only system CSRs at addresses 100h and above are accessible to the EEPROM Loader (with the addition of the PHY Management Interface Data Register (PMI_DATA) and PHY Management Interface Access Register (PMI_ACCESS) at addresses A4 and A8 respectively).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet DIGITAL_RST, nRST, POR, RELOAD EPC_BUSY = 1 Read Byte 0 Byte 0 = A5h N Load PHY registers with current straps Y Read Bytes 1-6 EPC_BUSY = 0 Write Bytes 1-6 into Host MAC and switch MAC Address Registers Soft Reset N Read Byte 7-11 Y EPC_BUSY = 1 Byte 7 = A5h N Load PHY registers with current straps Read Byte 0 Y Byte 0 = A5h Write Bytes 8-11 into Configuration Strap registers N Y Read Bytes 1-6 Write Byte
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.4.2 EEPROM Valid Flag Following the release of nRST, POR, DIGITAL_RST, or a RELOAD command, the EEPROM Loader starts by reading the first byte of data from the EEPROM. If the value of A5h is not read from the first byte, the EEPROM Loader will load the current configuration strap values into the PHY registers (see Section 10.2.4.4.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet The Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) is written with the new defaults as detailed in Section 14.4.2.5, "Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)," on page 295. The Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) is written with the new defaults as detailed in Section 14.4.2.9, "Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)," on page 302.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8-bits number_of_bursts repeat (number_of_bursts) 16-bits {starting_address[9:2] / count[7:0]} repeat (count) 8-bits data[31:24], 8-bits data[23:16], 8-bits data[15:8], 8-bits data[7:0] Note: The starting address is a DWORD address. Appending two 0 bits will form the register address.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 11 IEEE 1588 Hardware Time Stamp Unit 11.1 Functional Overview The LAN9311/LAN9311i provides hardware support for the IEEE 1588 Precision Time Protocol (PTP), allowing clock synchronization with remote Ethernet devices, packet time stamping, and time driven event generation. Time stamping is supported on all ports, with an individual IEEE 1588 Time Stamp module connected to each port via the MII bus.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 11.1.2 Block Diagram The LAN9311/LAN9311i IEEE 1588 implementation is illustrated in Figure 11.1, and consists of the following major function blocks: IEEE 1588 Time Stamp These three identical blocks provide time stamping functions on all switch fabric ports. IEEE 1588 Clock This block provides a 64-bit tunable clock that is used as the time source for all IEEE 1588 time stamp related functions.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 11.2 IEEE 1588 Time Stamp The LAN9311/LAN9311i contains three identical IEEE 1588 Time Stamp blocks as shown in Figure 11.1. These blocks are responsible for capturing the source UUID, sequence ID, and current 64-bit IEEE 1588 clock time upon detection of a Sync or Delay_Req message type on their respective port. The mode of the clock (master or slave) determines which message is detected on receive and transmit.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Clock synchronization and hardware processing between the network data and the time stamp capture hardware causes the time stamp point to be slightly delayed. The host software can account for this delay, as it is fairly deterministic. Table 11.2 details the time stamp capture delay as a function of the mode of operation. Refer to Chapter 7, "Ethernet PHYs," on page 82 for details on these modes. Table 11.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 11.2.2 PTP Message Detection In order to provide the most flexibility, loose packet type matching is used by the LAN9311/LAN9311i. This assumes that for all packets received with a valid FCS, only the MAC destination address is required to qualify them as a PTP message. For Ethernet, four multicast addresses are specified in the PTP protocol: 224.0.1.129 through 224.0.1.132.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 11.3 IEEE 1588 Clock The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN9311/LAN9311i. It is readable and writable by the host via the 1588 Clock High-DWORD Register (1588_CLOCK_HI) and 1588 Clock Low-DWORD Register (1588_CLOCK_LO). In order to accurately read this clock, a special procedure must be followed.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 11.4 IEEE 1588 Clock/Events The IEEE 1588 Clock/Events block is responsible for generating and controlling all IEEE 1588 clock related events.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 12 General Purpose Timer & Free-Running Clock This chapter details the LAN9311/LAN9311i General Purpose Timer (GPT) and the Free-Running Clock. 12.1 General Purpose Timer The LAN9311/LAN9311i provides a 16-bit programmable General Purpose Timer that can be used to generate periodic system interrupts. The resolution of this timer is 100uS.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 13 GPIO/LED Controller 13.1 Functional Overview The GPIO/LED Controller provides 12 configurable general purpose input/output pins, GPIO[11:0]. These pins can be individually configured to function as inputs, push-pull outputs, or open drain outputs and each is capable of interrupt generation with configurable polarity.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 13.2.1 GPIO IEEE 1588 Timestamping Two of the GPIO pins, GPIO[9:8], have the option to be used for IEEE 1588 time stamp functions. This allows a time stamp capture to be triggered when the GPIO is configured as an input, or output a signal from the GPIO based on an IEEE 1588 clock target compare event when configured as an output.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet GPIO_INT_POL[9:8] bits also determine the polarity of the clock events as described in Section 13.2.1.2. 13.2.2.2 IEEE 1588 GPIO Interrupts In addition to the standard GPIO interrupts in the General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN), the IEEE 1588 timestamp enabled GPIO[9:8] pins contain the ability to generate and clear specific IEEE 1588 related interrupts.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 13.1 LED Operation as a Function of LED_CFG[9:8] (continued) LED_CFG[9:8] (LED_FUN[1:0]) nP1LED1 (GPIO1) Full-duplex / Collision Port 1 Full-duplex / Collision Port 1 Full-duplex / Collision Port 1 TXEN Port 1 nP1LED0 (GPIO0) Speed Port 1 10Link / Activity Port 1 Speed Port 1 RXDV Port 1 The various LED indication functions shown in Table 13.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 14 Register Descriptions This section describes the various LAN9311/LAN9311i control and status registers (CSR’s). These registers are broken into 5 categories. The following sections detail the functionality and accessibility of all the LAN9311/LAN9311i registers within each category: Section 14.1, "TX/RX FIFO Ports," on page 168 Section 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.1 TX/RX FIFO Ports The LAN9311/LAN9311i contains four host-accessible FIFO’s: TX Status, RX Status, TX Data, and RX Data. These FIFO’s store the incoming and outgoing address and data information, acting as a conduit between the host bus interface (HBI) and the Host MAC. The sizes of these FIFO’s are configurable via the Hardware Configuration Register (HW_CFG). Refer to Section 9.7.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2 System Control and Status Registers The System CSR’s are directly addressable memory mapped registers with a base address offset range of 050h to 2DCh. These registers are addressable by the Host via the Host Bus Interface (HBI). Table 14.1 lists the System CSR’s and their corresponding addresses in order. All system CSR’s are reset to their default value on the assertion of a chip-level reset.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.1 System Control and Status Registers (continued) ADDRESS OFFSET SYMBOL 09Ch FREE_RUN Free Running Counter Register, Section 14.2.9.7 0A0h RX_DROP Host MAC RX Dropped Frames Counter Register, Section 14.2.2.6 0A4h MAC_CSR_CMD 0A4h EEPROM Loader Access Only PMI_DATA 0A8h MAC_CSR_DATA Host MAC CSR Interface Data Register, Section 14.2.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.1 System Control and Status Registers (continued) ADDRESS OFFSET SYMBOL REGISTER NAME 13Ch 1588_SRC_UUID_LO_TX_CAPTURE_2 Port 2 1588 Source UUID Low-DWORD Transmit Capture Register, Section 14.2.5.8 140h 1588_CLOCK_HI_RX_CAPTURE_MII Port 0 1588 Clock High-DWORD Receive Capture Register, Section 14.2.5.1 144h 1588_CLOCK_LO_RX_CAPTURE_MII Port 0 1588 Clock Low-DWORD Receive Capture Register, Section 14.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.1 System Control and Status Registers (continued) ADDRESS OFFSET SYMBOL 1A0h MANUAL_FC_1 Port 1 Manual Flow Control Register, Section 14.2.6.1 1A4h MANUAL_FC_2 Port 2 Manual Flow Control Register, Section 14.2.6.2 1A8h MANUAL_FC_MII 1ACh SWITCH_CSR_DATA Switch Fabric CSR Interface Data Register, Section 14.2.6.4 1B0h SWITCH_CSR_CMD Switch Fabric CSR Interface Command Register, Section 14.2.6.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.1 Interrupts This section details the interrupt related System CSR’s. These registers control, configure, and monitor the IRQ interrupt output pin and the various LAN9311/LAN9311i interrupt sources. For more information on the LAN9311/LAN9311i interrupts, refer to Chapter 5, "System Interrupts," on page 49. 14.2.1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 4 IRQ Polarity (IRQ_POL) When cleared, this bit enables the IRQ line to function as an active low output. When set, the IRQ output is active high. When the IRQ is configured as an open-drain output (via the IRQ_TYPE bit), this bit is ignored, and the interrupt is always active low. R/W NASR 0b Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.1.2 Interrupt Status Register (INT_STS) Offset: 058h Size: 32 bits This register contains the current status of the generated interrupts. A value of 1 indicates the corresponding interrupt conditions have been met, while a value of 0 indicates the interrupt conditions have not been met.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION 19 GP Timer (GPT_INT) This interrupt is issued when the General Purpose Timer Count Register (GPT_CNT) wraps past zero to FFFFh. 18 RESERVED 17 Power Management Interrupt Event (PME_INT) This interrupt is issued when a Power Management Event is detected as configured in the Power Management Control Register (PMT_CTRL).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 4 RX Status FIFO Full Interrupt (RSFF) This interrupt is generated when the RX Status FIFO is full. R/WC 0b 3 RX Status FIFO Level Interrupt (RSFL) This interrupt is generated when the RX Status FIFO reaches the programmed level in the RX Status Level field of the FIFO Level Interrupt Register (FIFO_INT).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.1.3 Interrupt Enable Register (INT_EN) Offset: 05Ch Size: 32 bits This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 5 RESERVED - This bit must be written with 0b for proper operation. R/W 0b 4 RX Status FIFO Full Interrupt Enable (RSFF_EN) R/W 0b 3 RX Status FIFO Level Interrupt Enable (RSFL_EN) R/W 0b RESERVED RO - 2:0 SMSC LAN9311/LAN9311i 179 DATASHEET Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.1.4 FIFO Level Interrupt Register (FIFO_INT) Offset: 068h Size: 32 bits This read/write register configures the limits where the RX/TX Data and Status FIFO’s will generate system interrupts. BITS DESCRIPTION TYPE DEFAULT 31:24 TX Data Available Level The value in this field sets the level, in number of 64 Byte blocks, at which the TX Data FIFO Available Interrupt (TDFA) will be generated.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2 Host MAC & FIFO’s This section details the Host MAC and TX/RX FIFO related System CSR’s. These Host Bus Interface accessible registers allow for the configuration of the TX/RX FIFO’s, Host MAC and indirect access to the complete set of Host MAC CSR’s.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 14:13 RESERVED RO - 12:8 RX Data Offset (RXDOFF) This field controls the offset value, in bytes, that is added to the beginning of an RX data packet. The start of the valid data will be shifted by the number of bytes specified in this field. An offset of 0-31 bytes is a valid number of offset bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.2 Transmit Configuration Register (TX_CFG) Offset: 070h Size: 32 bits This register controls the Host MAC transmit functions. BITS TYPE DEFAULT RESERVED RO - 15 Force TX Status Discard (TXS_DUMP) When a 1 is written to this bit, the TX Status FIFO is cleared of all pending status DWORD’s and the TX status pointers are cleared to zero.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.3 Receive Datapath Control Register (RX_DP_CTRL) Offset: 078h Size: 32 bits This register is used to discard unwanted receive frames. BITS DESCRIPTION TYPE DEFAULT 31 RX Data FIFO Fast Forward (RX_FFWD) Writing a 1 to this bit causes the RX Data FIFO to fast-forward to the start of the next frame. This bit will remain high until the RX Data FIFO fastforward operation has completed.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.4 RX FIFO Information Register (RX_FIFO_INF) Offset: 07Ch Size: 32 bits This register contains the indication of used space in the RX FIFO’s. BITS DESCRIPTION TYPE DEFAULT 31:24 RESERVED RO - 23:16 RX Status FIFO Used Space (RXSUSED) This field indicates the amount of space, in DWORD’s, currently used in the RX Status FIFO.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.5 TX FIFO Information Register (TX_FIFO_INF) Offset: 080h Size: 32 bits This register contains the indication of free space in the TX Data FIFO and the used space in the TX Status FIFO. BITS DESCRIPTION TYPE DEFAULT 31:24 RESERVED RO - 23:16 TX Status FIFO Used Space (TXSUSED) This field indicates the amount of space, in DWORD’s, currently used in the TX Status FIFO.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.6 Host MAC RX Dropped Frames Counter Register (RX_DROP) Offset: 0A0h Size: 32 bits This register indicates the number of receive frames that have been dropped by the Host MAC. BITS 31:0 DESCRIPTION RX Dropped Frame Counter (RX_DFC) This counter is incremented every time a receive frame is dropped by the Host MAC. RX_DFC is cleared on any read of this register.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD) Offset: 0A4h Size: 32 bits This read-write register is used to control the read and write operations to/from the Host MAC. This register in used in conjunction with the Host MAC CSR Interface Data Register (MAC_CSR_DATA) to indirectly access the Host MAC CSR’s. Note: The full list of Host MAC CSR’s are described in Section 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.8 Host MAC CSR Interface Data Register (MAC_CSR_DATA) Offset: 0A8h Size: 32 bits This read-write register is used in conjunction with the Host MAC CSR Interface Command Register (MAC_CSR_CMD) to indirectly access the Host MAC CSR’s. Note: The full list of Host MAC CSR’s are described in Section 14.3, "Host MAC Control and Status Registers," on page 271.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.9 Host MAC Automatic Flow Control Configuration Register (AFC_CFG) Offset: 0ACh Size: 32 bits This read/write register configures the mechanism that controls the automatic and software-initiated transmission of pause frames and back pressure from the Host MAC to the switch fabric. This register is used in conjunction with the Host MAC Flow Control Register (HMAC_FLOW) in the Host MAC CSR space.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 3 Flow Control on Multicast Frame (FCMULT) When this bit is set, the Host MAC will assert back pressure when the AFC level is reached and a multicast frame is received. This field has no function in full-duplex mode.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.2 Backpressure Duration Bit Mapping (continued) BACKPRESSURE DURATION 9h 300uS 302.2uS Ah 350uS 352.2uS Bh 400uS 402.2uS Ch 450uS 452.2uS Dh 500uS 502.2uS Eh 550uS 552.2uS Fh 600uS 602.2uS Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.3 GPIO/LED This section details the General Purpose I/O (GPIO) and LED related System CSR’s. 14.2.3.1 General Purpose I/O Configuration Register (GPIO_CFG) Offset: 1E0h Size: 32 bits This read/write register configures the GPIO input and output pins. The polarity of the 12 GPIO pins is configured here as well as the IEEE 1588 timestamping and clock compare event output properties of the GPIO[9:8] pins.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 11:0 DESCRIPTION GPIO Buffer Type 11-0 (GPIOBUF[11:0]) This field sets the buffer types of the 12 GPIO pins.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.3.2 General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) Offset: 1E4h Size: 32 bits This read/write register configures the direction of the 12 GPIO pins and contains the GPIO input and output data bits. BITS DESCRIPTION TYPE DEFAULT 31:28 RESERVED RO - 27:16 GPIO Direction 11-0 (GPIODIR[11:0]) These bits set the input/output direction of the 12 GPIO pins.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.3.3 General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) Offset: 1E8h Size: 32 bits This read/write register contains the GPIO interrupt status bits. Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these interrupt bits are cascaded into bit 12 (GPIO) of the Interrupt Status Register (INT_STS).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.3.4 LED Configuration Register (LED_CFG) Offset: 1BCh Size: 32 bits This read/write register configures the GPIO[7:0] pins as LED[7:0] pins and sets their functionality. BITS 31:10 9:8 DESCRIPTION TYPE DEFAULT RESERVED RO - LED Function 1-0 (LED_FUN[1:0]) These bits control the function associated with each LED pin as shown in Table 13.1 of Section 13.3, "LED Operation," on page 165. R/W Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.4 EEPROM This section details the EEPROM related System CSR’s. These registers should only be used if an EEPROM has been connected to the LAN9311/LAN9311i. Refer to chapter Section 10.2, "I2C/Microwire Master EEPROM Controller," on page 138 for additional information on the various modes (I2C and Microwire) of the EEPROM Controller (EPC). 14.2.4.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 30:28 EEPROM Controller Command (EPC_COMMAND) This field is used to issue commands to the EEPROM controller. The EEPROM controller will execute a command when the EPC_BUSY bit is set. A new command must not be issued until the previous command completes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 18 EEPROM Loader Address Overflow (LOADER_OVERFLOW) This bit indicates that the EEPROM Loader tried to read past the end of the EEPROM address space. This indicates misconfigured EEPROM data. RO 0b R/WC 0b RO 0b R/W 0000h This bit is cleared when the EEPROM Loader is restarted with a RELOAD command, Soft Reset(SRST), or a Digital Reset(DIGITAL_RST).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.4.2 EEPROM Data Register (E2P_DATA) Offset: 1B8h Size: 32 bits This read/write register is used in conjunction with the EEPROM Command Register (E2P_CMD) to perform read and write operations with the serial EEPROM. BITS DESCRIPTION TYPE DEFAULT 31:8 RESERVED RO - 7:0 EEPROM Data (EEPROM_DATA) This field contains the data read from or written to the EEPROM.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5 IEEE 1588 This section details the IEEE 1588 timestamp related registers. Each port of the LAN9311/LAN9311i has a 1588 timestamp block with 8 related registers, 4 for transmit capture and 4 for receive capture. These sets of registers are identical in functionality for each port, and thus their register descriptions have been consolidated.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.2 Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x) Offset: Port 1: 104h Port 2: 124h Port 0: 144h Size: 32 bits BITS DESCRIPTION TYPE DEFAULT 31:0 Timestamp Low (TS_LO) This field contains the low 32-bits of the timestamp taken on the receipt of a 1588 Sync or Delay_Req packet.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.3 Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register (1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x) Offset: BITS Port 1: 108h Port 2: 128h Port 0: 148h Size: 32 bits DESCRIPTION TYPE DEFAULT 31:16 Sequence ID (SEQ_ID) This field contains the Sequence ID from the 1588 Sync or Delay_Req packet.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.4 Port x 1588 Source UUID Low-DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x) Offset: Port 1: 10Ch Port 2: 12Ch Port 0: 14Ch Size: 32 bits BITS DESCRIPTION TYPE DEFAULT 31:0 Source UUID Low (SRC_UUID_LO) This field contains the low 32-bits of the Source UUID from the 1588 Sync or Delay_Req packet.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.5 Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x) Offset: BITS 31:0 Port 1: 110h Port 2: 130h Port 0: 150h Size: DESCRIPTION Timestamp High (TS_HI) This field contains the high 32-bits of the timestamp taken on the transmission of a 1588 Sync or Delay_Req packet.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.6 Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x) Offset: BITS 31:0 Port 1: 114h Port 2: 134h Port 0: 154h Size: DESCRIPTION Timestamp Low (TS_LO) This field contains the low 32-bits of the timestamp taken on the transmission of a 1588 Sync or Delay_Req packet.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.7 Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x) Offset: BITS Port 1: 118h Port 2: 138h Port 0: 158h Size: 32 bits DESCRIPTION TYPE DEFAULT 31:16 Sequence ID (SEQ_ID) This field contains the Sequence ID from the 1588 Sync or Delay_Req packet.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.8 Port x 1588 Source UUID Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x) Offset: Port 1: 11Ch Port 2: 13Ch Port 0: 15Ch Size: 32 bits BITS DESCRIPTION TYPE DEFAULT 31:0 Source UUID Low (SRC_UUID_TX_LO) This field contains the low 32-bits of the Source UUID from the 1588 Sync or Delay_Req packet.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.9 GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8) Offset: 160h Size: 32 bits This read only register combined with the GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8) form the 64-bit GPIO 8 timestamp capture. BITS DESCRIPTION TYPE DEFAULT 31:0 Timestamp High (TS_HI) This field contains the high 32-bits of the timestamp upon activation of GPIO 8.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.10 GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8) Offset: 164h Size: 32 bits This read only register combined with the GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8) form the 64-bit GPIO 8 timestamp capture. BITS DESCRIPTION TYPE DEFAULT 31:0 Timestamp Low (TS_LO) This field contains the low 32-bits of the timestamp upon activation of GPIO 8.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.11 GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9) Offset: 168h Size: 32 bits This read only register combined with the GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9) form the 64-bit GPIO 9 timestamp capture. BITS DESCRIPTION TYPE DEFAULT 31:0 Timestamp High (TS_HI) This field contains the high 32-bits of the timestamp upon activation of GPIO 9.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.12 GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9) Offset: 16Ch Size: 32 bits This read only register combined with the GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9) form the 64-bit GPIO 9 timestamp capture. BITS DESCRIPTION TYPE DEFAULT 31:0 Timestamp Low (TS_LO) This field contains the low 32-bits of the timestamp upon activation of GPIO 9.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.13 1588 Clock High-DWORD Register (1588_CLOCK_HI) Offset: 170h Size: 32 bits This read/write register combined with 1588 Clock Low-DWORD Register (1588_CLOCK_LO) form the 64-bit 1588 Clock value. The 1588 Clock value is used for all 1588 timestamping. The 1588 Clock has a base frequency of 100MHz, which can be adjusted via the 1588 Clock Addend Register (1588_CLOCK_ADDEND) accordingly.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.14 1588 Clock Low-DWORD Register (1588_CLOCK_LO) Offset: 174h Size: 32 bits This read/write register combined with 1588 Clock High-DWORD Register (1588_CLOCK_HI) form the 64-bit 1588 Clock value. The 1588 Clock value is used for all 1588 timestamping. The 1588 Clock has a base frequency of 100MHz, which can be adjusted via the 1588 Clock Addend Register (1588_CLOCK_ADDEND) accordingly.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.15 1588 Clock Addend Register (1588_CLOCK_ADDEND) Offset: 178h Size: 32 bits This read/write register is responsible for adjusting the 64-bit 1588 Clock frequency. Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 155 for details on how to properly use this register.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.16 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI) Offset: 17Ch Size: 32 bits T h i s r e a d / w r i t e r e g i s t e r c o m b i n e d w i t h 1 5 8 8 C l o c k Ta r g e t L o w - D W O R D R e g i s t e r (1588_CLOCK_TARGET_LO) form the 64-bit 1588 Clock Target value. The 1588 Clock Target value is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.17 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) Offset: 180h Size: 32 bits T h i s r e a d / w r i t e r e g i s t e r c o m b i n e d w i t h 1 5 8 8 C l o c k Ta r g e t H i g h - D W O R D R e g i s t e r (1588_CLOCK_TARGET_HI) form the 64-bit 1588 Clock Target value. The 1588 Clock Target value is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.18 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) Offset: 184h Size: 32 bits This read/write register combined with 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO) form the 64-bit 1588 Clock Target Reload value.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.19 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO) Offset: 188h Size: 32 bits This read/write register combined with 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) form the 64-bit 1588 Clock Target Reload value. The 1588 Clock Target Reload is the value that is reloaded or added to the 1588 Clock Compare value when a clock compare event occurs.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.20 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) Offset: 18Ch Size: 32 bits This read/write register combined with the 1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO) forms the 48-bit Auxiliary (user defined) MAC address.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.21 1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO) Offset: 190h Size: 32 bits This read/write register combined with the 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) forms the 48-bit Auxiliary (user defined) MAC address.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.22 1588 Configuration Register (1588_CONFIG) Offset: 194h Size: 32 bits This read/write register is responsible for the configuration of the 1588 timestamps for all ports. BITS DESCRIPTION TYPE DEFAULT 31 Master/Slave Port 2 (M_nS_2) When set, Port 2 is a time clock master and captures timestamps when a Sync packet is transmitted and when a Delay_Req is received.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 22 DESCRIPTION Primary MAC Address Enable Port 1 (MAC_PRI_EN_1) This bit enables/disables the primary MAC address on Port 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 13 DESCRIPTION Alternate MAC Address 1 Enable Port 0(Host MAC) (MAC_ALT1_EN_MII) This bit enables/disables the alternate MAC address 1 on Port 0.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 5 Lock Enable GPIO 8 (LOCK_GPIO_8) This bit enables/disables the GPIO 8 lock. This lock prevents a 1588 capture from overwriting the Clock value if the 1588_GPIO8 interrupt in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) is already set due to a previous capture.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.23 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) Offset: 198h Size: 32 bits This read/write register contains the IEEE 1588 interrupt status and enable bits. Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these interrupt bits are cascaded into bit 29 (1588_EVNT) of the Interrupt Status Register (INT_STS).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 3 1588 Port 0(Host MAC) TX Interrupt (1588_MII_TX_INT) This interrupt indicates that a packet from the Host MAC to the switch fabric matches the configured PTP packet and the 1588 clock was captured. R/WC 0b R/WC 0b R/WC 0b R/WC 0b Note: 2 1588 GPIO9 Interrupt (1588_GPIO9_INT) This interrupt indicates that an event on GPIO9 occurred and the 1588 clock was captured.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.24 1588 Command Register (1588_CMD) Offset: 19Ch Size: 32 bits This register is used to issue 1588 commands. Using the clock snapshot bit allows the host to properly read the current IEEE 1588 clock values from the 1588 Clock High-DWORD Register (1588_CLOCK_HI) and 1588 Clock Low-DWORD Register (1588_CLOCK_LO). Refer to section Section 11.3, "IEEE 1588 Clock," on page 160 for additional information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.6 Switch Fabric This section details the memory mapped System CSR’s which are related to the Switch Fabric. The flow control of all three ports of the switch fabric can be configured via the memory mapped System CSR’s MANUAL_FC_1, MANUAL_FC_2 and MANUAL_FC_MII. The MAC address used by the switch for Pause frames is configured via the SWITCH_MAC_ADDRH and SWITCH_MAC_ADDRL registers.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 1 Port 1 Full-Duplex Transmit Flow Control Enable (TX_FC_1) When the MANUAL_FC_1 bit is set, or Auto-Negotiation is disabled, this bit enables/disables full-duplex Pause packets to be generated on switch Port 1. R/W Note 14.6 R/W Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.6.2 Port 2 Manual Flow Control Register (MANUAL_FC_2) Offset: 1A4h Size: 32 bits This read/write register allows for the manual configuration of the switch Port 2 flow control. This register also provides read back of the currently enabled flow control settings, whether set manually or Auto-Negotiated. Refer to Section 6.2.3, "Flow Control Enable Logic," on page 58 for additional information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Note 14.8 The default value of this field is determined by the BP_EN_strap_2 configuration strap. The strap values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the values, this register is updated with the new values. See Section 4.2.4, "Configuration Straps," on page 40 for more information. Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.6.3 Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII) Offset: 1A8h Size: 32 bits This read/write register allows for the manual configuration of the switch Port 0(Host MAC) flow control. This register also provides read back of the currently enabled flow control settings, whether set manually or Auto-Negotiated. Refer to Section 6.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 1 Port 0 Transmit Flow Control Enable (TX_FC_MII) When the MANUAL_FC_MII bit is set, or Virtual Auto-Negotiation is disabled, this bit enables/disables full-duplex Pause packets to be generated on switch Port 0. R/W Note 14.14 R/W Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.6.4 Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) Offset: 1ACh Size: 32 bits This read/write register is used in conjunction with the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) to perform read and write operations with the Switch Fabric CSR’s. Refer to Section 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.6.5 Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) Offset: 1B0h Size: 32 bits This read/write register is used in conjunction with the Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) to control the read and write operations to the various Switch Fabric CSR’s. Refer to Section 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 19:16 CSR Byte Enable (CSR_BE[3:0]) This field is a 4-bit byte enable used for selection of valid bytes during write operations. Bytes which are not selected will not be written to the corresponding Switch Engine CSR.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.6.6 Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) Offset: 1F0h Size: 32 bits This register contains the upper 16-bits of the MAC address used by the switch for Pause frames. This register is used in conjunction with Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.6.7 Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL) Offset: 1F4h Size: 32 bits This register contains the lower 32-bits of the MAC address used by the switch for Pause frames. This register is used in conjunction with Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.6.8 Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) Offset: 200h - 2DCh Size: 32 bits This write-only register set is used to perform directly addressed write operations to the Switch Fabric CSR’s. Using this set of registers, writes can be directly addressed to select Switch Fabric registers, as specified in Table 14.3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.7 PHY Management Interface (PMI) The PMI registers are used (by the EEPROM Loader only) to indirectly access the PHY registers. Refer to Section 14.4, "Ethernet PHY Control and Status Registers," on page 287 for additional information on the PHY registers. Note: These registers are only accessible by the EEPROM Loader and NOT by the Host bus. Refer to Section 10.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.7.2 PHY Management Interface Access Register (PMI_ACCESS) Offset: 0A8h EEPROM Loader Access Only Size: 32 bits This register is used to control the management cycles to the PHYs. A PHY access is initiated when this register is written. This register is used in conjunction with the PHY Management Interface Data Register (PMI_DATA) to perform write operations to the PHYs.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8 Virtual PHY This section details the Virtual PHY System CSR’s. These registers provide status and control information similar to that of a real PHY while maintaining IEEE 802.3 compatibility. The Virtual PHY registers are addressable via the memory map, as described in Table 14.1, as well as serially via the MII management protocol (IEEE 802.3 clause 22).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.1 Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) Offset: Index (decimal): 1C0h 0 Size: 32 bits This read/write register is used to configure the Virtual PHY. Note: This register is re-written in its entirety by the EEPROM Loader following the release or reset or a RELOAD command. Refer to Section 10.2.4, "EEPROM Loader," on page 150 for more information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 7 DESCRIPTION TYPE DEFAULT R/W 0b Speed Select MSB (VPHY_SPEED_SEL_MSB) This bit is not used by the Virtual PHY and has no effect. The value returned is always 0. RO 0b RESERVED RO - Collision Test (VPHY_COL_TEST) This bit enables/disables the collision test mode. When set, the collision signal to the Host MAC is active during transmission from the Host MAC.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.2 Virtual PHY Basic Status Register (VPHY_BASIC_STATUS) Offset: Index (decimal): 1C4h 1 Size: 32 bits This register is used to monitor the status of the Virtual PHY. BITS 31:16 15 DESCRIPTION TYPE DEFAULT RESERVED (See Note 14.17) RO - 100BASE-T4 This bit displays the status of 100BASE-T4 compatibility. RO 0b Note 14.18 RO 1b RO 1b RO 1b RO 1b RO 0b Note 14.18 RO 0b Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 6 MF Preamble Suppression This bit indicates whether the Virtual PHY accepts management frames with the preamble suppressed. RO 0b RO 1b Note 14.20 RO 0b Note 14.21 RO 1b RO 1b Note 14.21 RO 0b Note 14.21 RO 1b Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.3 Virtual PHY Identification MSB Register (VPHY_ID_MSB) Offset: Index (decimal): 1C8h 2 Size: 32 bits This read/write register contains the MSB of the Virtual PHY Organizationally Unique Identifier (OUI). The LSB of the Virtual PHY OUI is contained in the Virtual PHY Identification LSB Register (VPHY_ID_LSB). BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED (See Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.4 Virtual PHY Identification LSB Register (VPHY_ID_LSB) Offset: Index (decimal): 1CCh 3 Size: 32 bits This read/write register contains the LSB of the Virtual PHY Organizationally Unique Identifier (OUI). The MSB of the Virtual PHY OUI is contained in the Virtual PHY Identification MSB Register (VPHY_ID_MSB). BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED (See Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.5 Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) Offset: Index (decimal): 1D0h 4 Size: 32 bits This read/write register contains the advertised ability of the Virtual PHY and is used in the AutoNegotiation process with the link partner. Note: This register is re-written in its entirety by the EEPROM Loader following the release or reset or a RELOAD command. Refer to Section 10.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 5 DESCRIPTION 10BASE-T Half Duplex This bit determines the advertised 10BASE-T half duplex capability. TYPE DEFAULT R/W 1b R/W 00001b Note 14.32 0: 10BASE-T half duplex ability not advertised 1: 10BASE-T half duplex ability advertised 4:0 Selector Field This field identifies the type of message being sent by Auto-Negotiation. 00001: IEEE 802.3 Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.6 Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) Offset: Index (decimal): 1D4h 5 Size: 32 bits This read-only register contains the advertised ability of the link partner’s PHY and is used in the AutoNegotiation process with the Virtual PHY.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 7 DESCRIPTION 100BASE-X Half Duplex This bit indicates the emulated link partner PHY 100BASE-X half duplex capability. TYPE DEFAULT RO Note 14.36 RO Note 14.36 RO Note 14.36 RO 00001b 0: 100BASE-X half duplex ability not supported 1: 100BASE-X half duplex ability supported 6 10BASE-T Full Duplex This bit indicates the emulated link partner PHY 10BASE-T full duplex capability.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.7 Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) Offset: Index (decimal): 1D8h 6 Size: 32 bits This register is used in the Auto-Negotiation process. BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED (See Note 14.37) RO - 15:5 RESERVED RO - Parallel Detection Fault This bit indicates whether a Parallel Detection Fault has been detected. This bit is always 0. RO 0b Note 14.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.8 Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) Offset: Index (decimal): 1DCh 31 Size: 32 bits This read/write register contains a current link speed/duplex indicator and SQE control. BITS TYPE DEFAULT RESERVED (See Note 14.42) RO - 15 RESERVED RO - 14 Switch Looopback MII When set, transmissions from the switch fabric Port 0(Host MAC) are not sent to the Host MAC.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Note 14.42 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide. Note 14.43 The default value of this field is the result of the Auto-Negotiation process if the AutoNegotiation (VPHY_AN) bit of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is set.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.9 Miscellaneous This section details the remainder of the System CSR’s. These registers allow for monitoring and configuration of various LAN9311/LAN9311i functions such as the Chip ID/revision, byte order testing, power management, hardware configuration, general purpose timer, and free running counter. 14.2.9.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.9.2 Byte Order Test Register (BYTE_TEST) Offset: 064h Size: 32 bits This read-only register can be used to determine the byte ordering of the current configuration. Byte ordering is a function of the host data bus width and endianess. Refer to Section 8.3, "Host Data Bus," on page 99 and Section 8.4, "Host Endianess," on page 100 for additional information on byte ordering.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.9.3 Hardware Configuration Register (HW_CFG) Offset: 074h Size: 32 bits This register allows the configuration of various hardware features including TX/RX FIFO sizes, Host MAC transmit threshold properties, and software reset. A detailed explanation of the allowable settings for FIFO memory allocation can be found in Section 9.7.3, "FIFO Memory Allocation Configuration," on page 122.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 19:16 TX FIFO Size (TX_FIF_SZ) This field sets the size of the TX FIFOs in 1KB values to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the space allocated by TX_FIF_SIZ, and the TX Data FIFO consumes the remaining space specified by TX_FIF_SZ. The minimum size of the TX FIFOs is 2KB (TX Data FIFO and Status FIFO combined).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.9.4 Power Management Control Register (PMT_CTRL) Offset: 084h Size: 32 bits This read-write register controls the power management features and the PME pin of the LAN9311/LAN9311i. The ready state of the LAN9311/LAN9311i can be determined via the Device Ready (READY) bit of this register. Refer to Section 4.3, "Power Management," on page 46 for additional information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 9 Wake-On-LAN Enable (WOL_EN) When set, the PME signal (if enabled via the PME_EN bit) will be asserted in accordance with the PME_IND bit upon a WOL event. When set, the PME_INT bit in the Interrupt Status Register (INT_STS) will also be asserted upon a WOL event, regardless of the setting of the PME_EN bit.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 0 Device Ready (READY) When set, this bit indicates that the LAN9311/LAN9311i is ready to be accessed. Upon power-up, nRST reset, soft reset, or digital reset, the host processor may interrogate this field as an indication that the LAN9311/LAN9311i has stabilized and is fully active. RO 0b This bit can cause an interrupt if enabled.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.9.5 General Purpose Timer Configuration Register (GPT_CFG) Offset: 08Ch Size: 32 bits This read/write register configures the LAN9311/LAN9311i General Purpose Timer (GPT). The GPT can be configured to generate host interrupts at the interval defined in this register. The current value of the GPT can be monitored via the General Purpose Timer Count Register (GPT_CNT). Refer to Section 12.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.9.6 General Purpose Timer Count Register (GPT_CNT) Offset: 090h Size: 32 bits This read-only register reflects the current general purpose timer (GPT) value. The register should be used in conjunction with the General Purpose Timer Configuration Register (GPT_CFG) to configure and monitor the GPT. Refer to Section 12.1, "General Purpose Timer," on page 162 for additional information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.9.7 Free Running 25MHz Counter Register (FREE_RUN) Offset: 09Ch Size: 32 bits This read-only register reflects the current value of the free-running 25MHz counter. Refer to Section 12.2, "Free-Running Clock," on page 162 for additional information. BITS DESCRIPTION TYPE DEFAULT 31:0 Free Running Counter (FR_CNT) This field reflects the current value of the free-running 32-bit counter.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.9.8 Reset Control Register (RESET_CTL) Offset: 1F8h Size: 32 bits This register contains software controlled resets. Note: This register can be read while the LAN9311/LAN9311i is in the reset or not ready states. Note: Either half of this register can be read without the need to read the other half.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3 Host MAC Control and Status Registers This section details the Host MAC System CSR’s. These registers are located in the Host MAC and are accessed indirectly via the HBI system CSR’s. Table 14.6 lists Host MAC registers that are accessible through the indexing method using the Host MAC CSR Interface Command Register (MAC_CSR_CMD) and Host MAC CSR Interface Data Register (MAC_CSR_DATA).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.1 Host MAC Control Register (HMAC_CR) Offset: 1h Size: 32 bits This read/write register establishes the RX and TX operation modes and controls for address filtering and packet filtering. Refer to Chapter 9, "Host MAC," on page 113 for additional information. Bits 19-15, 13, and 11 determine if the Host MAC accepts the packets from the switch fabric.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 16 Pass Bad Frames (PASSBAD) When set, all incoming frames that passed address filtering are received, including runt frames and collided frames. Refer to Section 9.4, "Address Filtering," on page 115 for additional information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 7:6 BackOff Limit (BOLMT) The BOLMT bits allow the user to set the back-off limit in a relaxed or aggressive mode. According to IEEE 802.3, the Host MAC has to wait for a random number [r] of slot-times(see note) after it detects a collision, where: (eq.1)0 < r < 2K The exponent K is dependent on how many times the current frame to be transmitted has been retried, as follows: (eq.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.2 Host MAC Address High Register (HMAC_ADDRH) Offset: 2h Size: 32 bits This read/write register contains the upper 16-bits of the physical address of the Host MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0]) is loaded from address 05h of the EEPROM.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.3 Host MAC Address Low Register (HMAC_ADDRL) Offset: 3h Size: 32 bits This read/write register contains the lower 32-bits of the physical address of the Host MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0]) is loaded from address 01h of the EEPROM.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.4 Host MAC Multicast Hash Table High Register (HMAC_HASHH) Offset: 4h Size: 32 bits The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the Hash table. The most significant bit determines the register to be used (Hi/Low), while the other five bits determine the bit within the register.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL) Offset: 5h Size: 32 bits This read/write register defines the lower 32-bits of the Multicast Hash Table. Please refer to the Host MAC Multicast Hash Table High Register (HMAC_HASHH) and Section 9.4, "Address Filtering" for more information. BITS 31:0 DESCRIPTION Lower 32-bits of the 64-bit Hash Table Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.6 Host MAC MII Access Register (HMAC_MII_ACC) Offset: 6h Size: 32 bits This read/write register is used in conjunction with the Host MAC MII Data Register (HMAC_MII_DATA) to access the internal PHY registers. Refer to Section 14.4, "Ethernet PHY Control and Status Registers" for a list of accessible PHY registers and PHY address information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.7 Host MAC MII Data Register (HMAC_MII_DATA) Offset: 7h Size: 32 bits This read/write register is used in conjunction with the Host MAC MII Access Register (HMAC_MII_ACC) to access the internal PHY registers. This register contains either the data to be written to the PHY register specified in the HMAC_MII_ACC Register, or the read data from the PHY register whose index is specified in the HMAC_MII_ACC Register.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.8 Host MAC Flow Control Register (HMAC_FLOW) Offset: 8h Size: 32 bits This read/write register controls the generation and reception of the Control (Pause command) frames by the Host MAC’s flow control block. The control frame fields are selected as specified in the 802.3 Specification and the Pause-Time value from this register is used in the “Pause Time” field of the control frame.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 0 Flow Control Busy (FCBSY) In full-duplex mode, this bit should read logical 0 before writing to the Host MAC Flow Control (HMAC_FLOW) register. To initiate a PAUSE control frame, the bit must be set. During a transfer of control frame, this bit continues to be set, signifying that a frame transmission is in progress.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1) Offset: 9h Size: 32 bits This read/write register contains the VLAN tag field to identify VLAN1 frames. When a VLAN1 frame is detected, the legal frame length is increased from 1518 bytes to 1522 bytes. Refer to Section 9.3, "Virtual Local Area Network (VLAN) Support," on page 114 for additional information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.10 Host MAC VLAN2 Tag Register (HMAC_VLAN2) Offset: Ah Size: 32 bits This read/write register contains the VLAN tag field to identify VLAN2 frames. When a VLAN2 frame is detected, the legal frame length is increased from 1518 bytes to 1538 bytes. Refer to Section 9.3, "Virtual Local Area Network (VLAN) Support," on page 114 for additional information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF) Offset: Bh Size: 32 bits This write-only register is used to configure the wake-up frame filter. Refer to Section 9.5, "Wake-up Frame Detection," on page 117 for additional information. BITS DESCRIPTION TYPE DEFAULT 31:0 Wake-Up Frame Filter (WFF) The Wake-up frame filter is configured through this register using an indexing mechanism.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.12 Host MAC Wake-up Control and Status Register (HMAC_WUCSR) Offset: Ch Size: 32 bits This read/write register contains data and control settings pertaining to the Host MAC’s remote wakeup status and capabilities. It is used in conjunction with the Host MAC Wake-up Frame Filter Register (HMAC_WUFF) to fully configure the wake-up frame filter. Refer to Section 9.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4 Ethernet PHY Control and Status Registers This section details the various LAN9311/LAN9311i Ethernet PHY control and status registers. The LAN9311/LAN9311i contains three PHY’s: Port 1 PHY, Port 2 PHY and a Virtual PHY. All PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management register set. All functionality and bit definitions comply with these standards. The IEEE 802.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers (continued) INDEX # SYMBOL 17 PHY_MODE_CONTROL_STATUS_x Port x PHY Mode Control/Status Register, Section 14.4.2.8 18 PHY_SPECIAL_MODES_x Port x PHY Special Modes Register, Section 14.4.2.9 27 PHY_SPECIAL_CONTROL_STAT_IND_x Port x PHY Special Control/Status Indication Register, Section 14.4.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.1 Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) Index (decimal): 0 Size: 16 bits This read/write register is used to configure the Port x PHY. Note: This register is re-written in its entirety by the EEPROM Loader following the release of reset or a RELOAD command. Refer to Section 10.2.4, "EEPROM Loader," on page 150 for additional information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 9 DESCRIPTION Restart Auto-Negotiation (PHY_RST_AN) When set, this bit restarts the Auto-Negotiation process. TYPE DEFAULT R/W SC 0b R/W Note 14.51 R/W 0b RO - 0: Normal operation 1: Auto-Negotiation restarted 8 Duplex Mode (PHY_DUPLEX) This bit is used to set the duplex when the Auto-Negotiation (PHY_AN) bit is disabled.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.2 Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) Index (decimal): 1 Size: 16 bits This register is used to monitor the status of the Port x PHY. BITS 15 DESCRIPTION TYPE DEFAULT RO 0b Note 14.52 RO 1b RO 1b RO 1b RO 1b RO 0b Note 14.52 RO 0b Note 14.52 RESERVED RO - Auto-Negotiation Complete This bit indicates the status of the Auto-Negotiation process.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 3 DESCRIPTION Auto-Negotiation Ability This bit indicates the status of the PHY’s auto-negotiation. TYPE DEFAULT RO 1b RO/LL 0b RO/LH 0b RO 1b 0: PHY is unable to perform auto-negotiation 1: PHY is able to perform auto-negotiation 2 Link Status This bit indicates the status of the link. 0: Link is down 1: Link is up 1 Jabber Detect This bit indicates the status of the jabber condition.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.3 Port x PHY Identification MSB Register (PHY_ID_MSB_x) Index (decimal): 2 Size: 16 bits This read/write register contains the MSB of the Organizationally Unique Identifier (OUI) for the Port x PHY. The LSB of the PHY OUI is contained in the Port x PHY Identification LSB Register (PHY_ID_LSB_x).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.4 Port x PHY Identification LSB Register (PHY_ID_LSB_x) Index (decimal): 3 Size: 16 bits This read/write register contains the LSB of the Organizationally Unique Identifier (OUI) for the Port x PHY. The MSB of the PHY OUI is contained in the Port x PHY Identification MSB Register (PHY_ID_MSB_x). BITS TYPE DEFAULT PHY ID This field is assigned to the 19th through 24th bits of the PHY OUI, respectively.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.5 Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) Index (decimal): 4 Size: 16 bits This read/write register contains the advertised ability of the Port x PHY and is used in the AutoNegotiation process with the link partner. Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD command. Refer to Section 10.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 4:0 DESCRIPTION TYPE DEFAULT R/W 00001b Selector Field This field identifies the type of message being sent by Auto-Negotiation. 00001: IEEE 802.3 Note 14.53 The Pause and Asymmetric Pause bits are loaded into the PHY registers by the EEPROM Loader. Note 14.54 The default value of this bit is determined by the Manual Flow Control Enable Strap (manual_FC_strap_x).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value autoneg_strap_x speed_strap_x Default 10BASE-T Half Duplex (Bit 5) Value 1 1 1 SMSC LAN9311/LAN9311i 297 DATASHEET Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.6 Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) Index (decimal): 5 Size: 16 bits This read-only register contains the advertised ability of the link partner’s PHY and is used in the AutoNegotiation process between the link partner and the Port x PHY. BITS 15 DESCRIPTION Next Page This bit indicates the link partner PHY page capability.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 6 DESCRIPTION 10BASE-T Full Duplex This bit indicates the link partner PHY 10BASE-T full duplex capability. TYPE DEFAULT RO 0b RO 0b RO 00001b Note 14.57 0: 10BASE-T full duplex ability not supported 1: 10BASE-T full duplex ability supported 5 10BASE-T Half Duplex This bit indicates the link partner PHY 10BASE-T half duplex capability.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.7 Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) Index (decimal): 6 Size: 16 bits This read/write register is used in the Auto-Negotiation process between the link partner and the Port x PHY. BITS 15:5 4 DESCRIPTION RESERVED Parallel Detection Fault This bit indicates whether a Parallel Detection Fault has been detected.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.8 Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) Index (decimal): 17 Size: 16 bits This read/write register is used to control and monitor various Port x PHY configuration options. BITS 15:14 13 DESCRIPTION TYPE DEFAULT RESERVED RO - Energy Detect Power-Down (EDPWRDOWN) This bit controls the Energy Detect Power-Down mode.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.9 Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) Index (decimal): 18 Size: 16 bits This read/write register is used to control the special modes of the Port x PHY. Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD command. Refer to Section 10.2.4, "EEPROM Loader," on page 150 for more information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.10 MODE[2:0] Definitions (continued) AFFECTED REGISTER BIT VALUES MODE[2:0] MODE DEFINITIONS PHY_BASIC_CONTROL_x PHY_AN_ADV_x [13,12,10,8] [8,7,6,5] 011 100BASE-TX Full Duplex. Auto-negotiation disabled. CRS is active during Receive. 1001 N/A 100 100BASE-TX Half Duplex is advertised. Autonegotiation enabled. CRS is active during Transmit & Receive. 1100 0100 101 Repeater mode.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.10 Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) Index (decimal): 27 Size: 16 bits This read/write register is used to control various options of the Port x PHY. BITS DESCRIPTION TYPE DEFAULT 15 Auto-MDIX Control (AMDIXCTRL) This bit is responsible for determining the source of Auto-MDIX control for Port x.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.11 Auto-MDIX Enable and Auto-MDIX State Bit Functionality Auto-MDIX Enable (Bit 14) Auto-MDIX State (Bit 13) MODE 0 0 Manual mode, no crossover 0 1 Manual mode, crossover 1 0 Auto-MDIX mode 1 1 RESERVED (do not use this state) SMSC LAN9311/LAN9311i 305 DATASHEET Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.11 Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) Index (decimal): 29 Size: 16 bits This read-only register is used to determine to source of various Port x PHY interrupts. All interrupt source bits in this register are read-only and latch high upon detection of the corresponding interrupt (if enabled). A read of this register clears the interrupts.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) Index (decimal): 30 Size: 16 bits This read/write register is used to enable or mask the various Port x PHY interrupts and is used in conjunction with the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.13 Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x) Index (decimal): 31 Size: 16 bits This read/write register is used to control and monitor various options of the Port x PHY. BITS 15:13 12 DESCRIPTION TYPE DEFAULT RESERVED RO - Autodone This bit indicates the status of the Auto-Negotiation on the Port x PHY.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5 Switch Fabric Control and Status Registers This section details the various LAN9311/LAN9311i switch control and status registers that reside within the switch fabric. The switch control and status registers allow configuration of each individual switch port, the switch engine, and buffer manager. Switch fabric related interrupts and resets are also controlled and monitored via the switch CSRs.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 0414h MAC_RX_256_TO_511_CNT_MII Port 0 MAC Receive 256 to 511 Byte Count Register, Section 14.5.2.7 0415h MAC_RX_512_TO_1023_CNT_MII Port 0 MAC Receive 512 to 1023 Byte Count Register, Section 14.5.2.8 0416h MAC_RX_1024_TO_MAX_CNT_MII Port 0 MAC Receive 1024 to Max Byte Count Register, Section 14.5.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL REGISTER NAME 0455h MAC_TX_65_TO_127_CNT_MII Port 0 MAC Transmit 65 to 127 Byte Count Register, Section 14.5.2.29 0456h MAC_TX_128_TO_255_CNT_MII Port 0 MAC Transmit 128 to 255 Byte Count Register, Section 14.5.2.30 0457h MAC_TX_256_TO_511_CNT_MII Port 0 MAC Transmit 256 to 511 Byte Count Register, Section 14.5.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 0812h MAC_RX_65_TO_127_CNT_1 Port 1 MAC Receive 65 to 127 Byte Count Register, Section 14.5.2.5 0813h MAC_RX_128_TO_255_CNT_1 Port 1 MAC Receive 128 to 255 Byte Count Register, Section 14.5.2.6 0814h MAC_RX_256_TO_511_CNT_1 Port 1 MAC Receive 256 to 511 Byte Count Register, Section 14.5.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL REGISTER NAME 0852h MAC_TX_PAUSE_CNT_1 Port 1 MAC Transmit Pause Count Register, Section 14.5.2.26 0853h MAC_TX_PKTOK_CNT_1 Port 1 MAC Transmit OK Count Register, Section 14.5.2.27 0854h MAC_RX_64_CNT_1 0855h MAC_TX_65_TO_127_CNT_1 Port 1 MAC Transmit 65 to 127 Byte Count Register, Section 14.5.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 0C10h MAC_RX_UNDSZE_CNT_2 0C11h MAC_RX_64_CNT_2 0C12h MAC_RX_65_TO_127_CNT_2 Port 2 MAC Receive 65 to 127 Byte Count Register, Section 14.5.2.5 0C13h MAC_RX_128_TO_255_CNT_2 Port 2 MAC Receive 128 to 255 Byte Count Register, Section 14.5.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 0C42h-0C50h RESERVED 0C51h MAC_TX_DEFER_CNT_2 Port 2 MAC Transmit Deferred Count Register, Section 14.5.2.25 0C52h MAC_TX_PAUSE_CNT_2 Port 2 MAC Transmit Pause Count Register, Section 14.5.2.26 0C53h MAC_TX_PKTOK_CNT_2 Port 2 MAC Transmit OK Count Register, Section 14.5.2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL REGISTER NAME Switch Engine CSRs 1800h SWE_ALR_CMD 1801h SWE_ALR_WR_DAT_0 Switch Engine ALR Write Data 0 Register, Section 14.5.3.2 1802h SWE_ALR_WR_DAT_1 Switch Engine ALR Write Data 1 Register, Section 14.5.3.3 1803h-1804h RESERVED 1805h SWE_ALR_RD_DAT_0 Switch Engine ALR Read Data 0 Register, Section 14.5.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL REGISTER NAME 1847h SWE_INGRESS_PORT_TYP 1848h SWE_BCST_THROT Switch Engine Broadcast Throttling Register, Section 14.5.3.23 1849h SWE_ADMT_N_MEMBER Switch Engine Admit Non Member Register, Section 14.5.3.24 184Ah SWE_INGRESS_RATE_CFG Switch Engine Ingress Rate Configuration Register, Section 14.5.3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 1C02h BM_FC_PAUSE_LVL 1C03h BM_FC_RESUME_LVL 1C04h BM_BCST_LVL 1C05h BM_DRP_CNT_SRC_MII Buffer Manager Port 0 Drop Count Register, Section 14.5.4.6 1C06h BM_DRP_CNT_SRC_1 Buffer Manager Port 1 Drop Count Register, Section 14.5.4.7 1C07h BM_DRP_CNT_SRC_2 Buffer Manager Port 2 Drop Count Register, Section 14.5.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 1C20h BM_IMR Buffer Manager Interrupt Mask Register, Section 14.5.4.26 1C21h BM_IPR Buffer Manager Interrupt Pending Register, Section 14.5.4.27 1C22h-FFFFh RESERVED SMSC LAN9311/LAN9311i REGISTER NAME Reserved for Future Use 319 DATASHEET Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.1 General Switch CSRs This section details the general switch fabric CSRs. These registers control the main reset and interrupt functions of the switch fabric. A list of the general switch CSRs and their corresponding register numbers is included in Table 14.12. 14.5.1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.1.2 Switch Reset Register (SW_RESET) Register #: 0001h Size: 32 bits This register contains the switch fabric global reset. Refer to Section 4.2, "Resets," on page 36 for more information. BITS 31:1 0 DESCRIPTION TYPE DEFAULT RESERVED RO - Switch Fabric Reset (SW_RESET) This bit is the global switch fabric reset. All switch fabric blocks are affected. This bit must be manually cleared.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.1.3 Switch Global Interrupt Mask Register (SW_IMR) Register #: 0004h Size: 32 bits This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch related interrupts in the Switch Global Interrupt Pending Register (SW_IPR) may be masked via this register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will unmask the interrupt.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.1.4 Switch Global Interrupt Pending Register (SW_IPR) Register #: 0005h Size: 32 bits This read-only register contains the pending global interrupts for the switch fabric. A set bit indicates an unmasked bit in the corresponding switch fabric sub-system has been triggered. All switch related interrupts in this register may be masked via the Switch Global Interrupt Mask Register (SW_IMR) register.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2 Switch Port 0, Port 1, and Port 2 CSRs This section details the switch Port 0(Host MAC), Port 1, and Port 2 CSRs. Each port provides a functionally identical set of registers which allow for the configuration of port settings, interrupts, and the monitoring of the various packet counters. Because the Port 0, Port 1, and Port 2 CSRs are functionally identical, their register descriptions have been consolidated.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.2 Port x MAC Receive Configuration Register (MAC_RX_CFG_x) Register #: Port0: 0401h Port1: 0801h Port2: 0C01h Size: 32 bits This read/write register configures the packet type passing parameters of the port. BITS DESCRIPTION TYPE DEFAULT 31:8 RESERVED RO - 7 RESERVED R/W 0b Note: This bit must always be written as 0.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.3 Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x) Register #: Port0: 0410h Port1: 0810h Port2: 0C10h Size: 32 bits This register provides a counter of undersized packets received by the port. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX Undersize Count of packets that have less than 64 byte and a valid FCS.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.4 Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x) Register #: Port0: 0411h Port1: 0811h Port2: 0C11h Size: 32 bits This register provides a counter of 64 byte packets received by the port. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX 64 Bytes Count of packets (including bad packets) that have exactly 64 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.5 Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x) Register #: Port0: 0412h Port1: 0812h Port2: 0C12h Size: 32 bits This register provides a counter of received packets between the size of 65 to 127 bytes. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX 65 to 127 Bytes Count of packets (including bad packets) that have between 65 and 127 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.6 Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x) Register #: Port0: 0413h Port1: 0813h Port2: 0C13h Size: 32 bits This register provides a counter of received packets between the size of 128 to 255 bytes. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX 128 to 255 Bytes Count of packets (including bad packets) that have between 128 and 255 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.7 Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x) Register #: Port0: 0414h Port1: 0814h Port2: 0C14h Size: 32 bits This register provides a counter of received packets between the size of 256 to 511 bytes. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX 256 to 511 Bytes Count of packets (including bad packets) that have between 256 and 511 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.8 Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x) Register #: Port0: 0415h Port1: 0815h Port2: 0C15h Size: 32 bits This register provides a counter of received packets between the size of 512 to 1023 bytes. The counter is cleared upon being read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.9 Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x) Register #: Port0: 0416h Port1: 0816h Port2: 0C16h Size: 32 bits This register provides a counter of received packets between the size of 1024 to the maximum allowable number bytes. The counter is cleared upon being read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.10 Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x) Register #: Port0: 0417h Port1: 0817h Port2: 0C17h Size: 32 bits This register provides a counter of received packets with a size greater than the maximum byte size. The counter is cleared upon being read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.11 Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x) Register #: Port0: 0418h Port1: 0818h Port2: 0C18h Size: 32 bits This register provides a counter of received packets that are or proper length and are free of errors. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX OK Count of packets that are of proper length and are free of errors.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x) Register #: Port0: 0419h Port1: 0819h Port2: 0C19h Size: 32 bits This register provides a counter of received packets that with CRC errors. The counter is cleared upon being read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.13 Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x) Register #: Port0: 041Ah Port1: 081Ah Port2: 0C1Ah Size: 32 bits This register provides a counter of valid received packets with a multicast destination address. The counter is cleared upon being read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.14 Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x) Register #: Port0: 041Bh Port1: 081Bh Port2: 0C1Bh Size: 32 bits This register provides a counter of valid received packets with a broadcast destination address. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX Broadcast Count of valid packets (proper length and free of errors) that have a broadcast destination address.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.15 Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x) Register #: Port0: 041Ch Port1: 081Ch Port2: 0C1Ch Size: 32 bits This register provides a counter of valid received pause frame packets. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX Pause Frame Count of valid packets (proper length and free of errors) that have a type field of 8808h and an op-code of 0001(Pause).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.16 Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x) Register #: Port0: 041Dh Port1: 081Dh Port2: 0C1Dh Size: 32 bits This register provides a counter of received packets of less than 64 bytes and a FCS error. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX Fragment Count of packets that have less than 64 bytes and a FCS error.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.17 Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x) Register #: Port0: 041Eh Port1: 081Eh Port2: 0C1Eh Size: 32 bits This register provides a counter of received packets with greater than the maximum allowable number of bytes and a FCS error. The counter is cleared upon being read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) Register #: Port0: 041Fh Port1: 081Fh Port2: 0C1Fh Size: 32 bits This register provides a counter of received packets with 64 bytes to the maximum allowable, and a FCS error. The counter is cleared upon being read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.19 Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x) Register #: Port0: 0420h Port1: 0820h Port2: 0C20h Size: 32 bits This register provides a counter of total bytes received. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX Bytes Count of total bytes received (including bad packets).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.20 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x) Register #: Port0: 0421h Port1: 0821h Port2: 0C21h Size: 32 bits This register provides a counter of total bytes received in good packets. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX Good Bytes Count of total bytes received in good packets (proper length and free of errors).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.21 Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x) Register #: Port0: 0422h Port1: 0822h Port2: 0C22h Size: 32 bits This register provides a counter of received packets with a symbol error. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX Symbol Count of packets that had a receive symbol error.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.22 Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x) Register #: Port0: 0423h Port1: 0823h Port2: 0C23h Size: 32 bits This register provides a counter of good packets with a type field of 8808h. The counter is cleared upon being read. BITS 31:0 DESCRIPTION RX Control Frame Count of good packets (proper length and free of errors) that have a type field of 8808h.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.23 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x) Register #: Port0: 0440h Port1: 0840h Port2: 0C40h Size: 32 bits This read/write register configures the transmit packet parameters of the port.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.24 Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) Register #: Port0: 0441h Port1: 0841h Port2: 0C41h Size: 32 bits This read/write register configures the flow control settings of the port. BITS DESCRIPTION TYPE DEFAULT 31:18 RESERVED RO - 17:16 Backoff Reset RX/TX Half duplex-only. Determines when the truncated binary exponential backoff attempts counter is reset.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.25 Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x) Register #: Port0: 0451h Port1: 0851h Port2: 0C51h Size: 32 bits This register provides a counter deferred packets. The counter is cleared upon being read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.26 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x) Register #: Port0: 0452h Port1: 0852h Port2: 0C52h Size: 32 bits This register provides a counter of transmitted pause packets. The counter is cleared upon being read. BITS 31:0 DESCRIPTION TX Pause Count of pause packets transmitted. Note: TYPE DEFAULT RC 00000000h This counter will stop at its maximum value of FFFF_FFFFh.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.27 Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x) Register #: Port0: 0453h Port1: 0853h Port2: 0C53h Size: 32 bits This register provides a counter of successful transmissions. The counter is cleared upon being read. BITS 31:0 DESCRIPTION TX OK Count of successful transmissions. Undersize packets are not included in this count.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.28 Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x) Register #: Port0: 0454h Port1: 0854h Port2: 0C54h Size: 32 bits This register provides a counter of 64 byte packets transmitted by the port. The counter is cleared upon being read. BITS DESCRIPTION 31:0 TX 64 Bytes Count of packets that have exactly 64 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.29 Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x) Register #: Port0: 0455h Port1: 0855h Port2: 0C55h Size: 32 bits This register provides a counter of transmitted packets between the size of 65 to 127 bytes. The counter is cleared upon being read. BITS 31:0 DESCRIPTION TX 65 to 127 Bytes Count of packets that have between 65 and 127 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.30 Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x) Register #: Port0: 0456h Port1: 0856h Port2: 0C56h Size: 32 bits This register provides a counter of transmitted packets between the size of 128 to 255 bytes. The counter is cleared upon being read. BITS 31:0 DESCRIPTION TX 128 to 255 Bytes Count of packets that have between 128 and 255 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.31 Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x) Register #: Port0: 0457h Port1: 0857h Port2: 0C57h Size: 32 bits This register provides a counter of transmitted packets between the size of 256 to 511 bytes. The counter is cleared upon being read. BITS 31:0 DESCRIPTION TX 256 to 511 Bytes Count of packets that have between 256 and 511 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.32 Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) Register #: Port0: 0458h Port1: 0858h Port2: 0C58h Size: 32 bits This register provides a counter of transmitted packets between the size of 512 to 1023 bytes. The counter is cleared upon being read. BITS 31:0 DESCRIPTION TX 512 to 1023 Bytes Count of packets that have between 512 and 1023 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.33 Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x) Register #: Port0: 0459h Port1: 0859h Port2: 0C59h Size: 32 bits This register provides a counter of transmitted packets between the size of 1024 to the maximum allowable number bytes. The counter is cleared upon being read. BITS 31:0 DESCRIPTION TX 1024 to Max Bytes Count of packets that have more than 1024 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.34 Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x) Register #: Port0: 045Ah Port1: 085Ah Port2: 0C5Ah Size: 32 bits This register provides a counter of undersized packets transmitted by the port. The counter is cleared upon being read. BITS 31:0 DESCRIPTION TX Undersize Count of packets that have less than 64 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.35 Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x) Register #: Port0: 045Ch Port1: 085Ch Port2: 0C5Ch Size: 32 bits This register provides a counter of total bytes transmitted. The counter is cleared upon being read. BITS DESCRIPTION TYPE DEFAULT 31:0 TX Bytes Count of total bytes transmitted (does not include bytes from collisions, but does include bytes from Pause packets).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.36 Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) Register #: Port0: 045Dh Port1: 085Dh Port2: 0C5Dh Size: 32 bits This register provides a counter of transmitted broadcast packets. The counter is cleared upon being read. BITS 31:0 DESCRIPTION TX Broadcast Count of broadcast packets transmitted.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.37 Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x) Register #: Port0: 045Eh Port1: 085Eh Port2: 0C5Eh Size: 32 bits This register provides a counter of transmitted multicast packets. The counter is cleared upon being read. BITS DESCRIPTION TYPE DEFAULT 31:0 TX Multicast Count of multicast packets transmitted including MAC Control Pause frames.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.38 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x) Register #: Port0: 045Fh Port1: 085Fh Port2: 0C5Fh Size: 32 bits This register provides a counter of transmitted packets which experienced a late collision. The counter is cleared upon being read. BITS DESCRIPTION TYPE DEFAULT 31:0 TX Late Collision Count of transmitted packets that experienced a late collision.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.39 Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x) Register #: Port0: 0460h Port1: 0860h Port2: 0C60h Size: 32 bits This register provides a counter of transmitted packets which experienced 16 collisions. The counter is cleared upon being read. BITS DESCRIPTION TYPE DEFAULT 31:0 TX Excessive Collision Count of transmitted packets that experienced 16 collisions.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.40 Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x) Register #: Port0: 0461h Port1: 0861h Port2: 0C61h Size: 32 bits This register provides a counter of transmitted packets which experienced exactly 1 collision. The counter is cleared upon being read. BITS 31:0 DESCRIPTION TX Excessive Collision Count of transmitted packets that experienced exactly 1 collision.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.41 Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x) Register #: Port0: 0462h Port1: 0862h Port2: 0C62h Size: 32 bits This register provides a counter of transmitted packets which experienced between 2 and 15 collisions. The counter is cleared upon being read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.42 Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x) Register #: Port0: 0463h Port1: 0863h Port2: 0C63h Size: 32 bits This register provides a counter of total collisions including late collisions. The counter is cleared upon being read. BITS DESCRIPTION TYPE DEFAULT 31:0 TX Total Collision Total count of collisions including late collisions.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x) Register #: Port0: 0480h Port1: 0880h Port2: 0C80h Size: 32 bits This register contains the Port x interrupt mask. Port x related interrupts in the Port x MAC Interrupt Pending Register (MAC_IPR_x) may be masked via this register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will unmask the interrupt.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x) Register #: Port0: 0481h Port1: 0881h Port2: 0C81h Size: 32 bits This read-only register contains the pending Port x interrupts. A set bit indicates an interrupt has been triggered. All interrupts in this register may be masked via the Port x MAC Interrupt Pending Register (MAC_IPR_x) register.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3 Switch Engine CSRs This section details the switch engine related CSRs. These registers allow configuration and monitoring of the various switch engine components including the ALR, VLAN, Port VID, and DIFFSERV tables. A list of the general switch CSRs and their corresponding register numbers is included in Table 14.12. 14.5.3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.2 Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) Register #: 1801h Size: 32 bits This register is used in conjunction with the Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) and contains the first 32 bits of ALR data to be manually written via the Make Entry command in the Switch Engine ALR Command Register (SWE_ALR_CMD).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.3 Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) Register #: 1802h Size: 32 bits This register is used in conjunction with the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) and contains the last 32 bits of ALR data to be manually written via the Make Entry command in the Switch Engine ALR Command Register (SWE_ALR_CMD).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 18:16 Port These bits indicate the port(s) associated with this MAC address. When bit 18 is cleared, a single port is selected. When bit 18 is set, multiple ports are selected.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.4 Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0) Register #: 1805h Size: 32 bits This register is used in conjunction with the Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) to read the ALR table. It contains the first 32 bits of the ALR entry and is loaded via the Get First Entry or Get Next Entry commands in the Switch Engine ALR Command Register (SWE_ALR_CMD).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.5 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) Register #: 1806h Size: 32 bits This register is used in conjunction with the Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0) to read the ALR table. It contains the last 32 bits of the ALR entry and is loaded via the Get First Entry or Get Next Entry commands in the Switch Engine ALR Command Register (SWE_ALR_CMD).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 18:16 Port These bits indicate the port(s) associated with this MAC address. When bit 18 is cleared, a single port is selected. When bit 18 is set, multiple ports are selected.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.6 Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) Register #: 1808h Size: 32 bits This register indicates the current ALR command status. BITS TYPE DEFAULT RESERVED RO - 1 ALR Init Done When set, indicates that the ALR table has finished being initialized by the reset process. The initialization is performed upon any reset that resets the switch fabric.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.7 Switch Engine ALR Configuration Register (SWE_ALR_CFG) Register #: 1809h Size: 32 bits This register controls the ALR aging timer duration. BITS 31:1 0 DESCRIPTION TYPE DEFAULT RESERVED RO - ALR Age Test When set, this bit decreases the aging timer from 5 minutes to 50mS. R/W 0b Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.8 Switch Engine VLAN Command Register (SWE_VLAN_CMD) Register #: 180Bh Size: 32 bits This register is used to read and write the VLAN or Port VID tables. A write to this address performs the specified access. For a read access, the Operation Pending bit in the Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) indicates when the command is finished.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.9 Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA) Register #: 180Ch Size: 32 bits This register is used write the VLAN or Port VID tables.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.10 Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) Register #: 180Eh Size: 32 bits This register is used to read the VLAN or Port VID tables.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.11 Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) Register #: 1810h Size: 32 bits This register indicates the current VLAN command status. BITS 31:1 0 DESCRIPTION TYPE DEFAULT RESERVED RO - Operation Pending When set, this bit indicates that the read or write command is taking place. This bit is cleared once the command has finished. RO SC 0b Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG) Register #: 1811h Size: 32 bits This register is used to read and write the DIFFSERV table. A write to this address performs the specified access. This table is used to map the received IP ToS/CS to a priority.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.13 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA) Register #: 1812h Size: 32 bits This register is used to write the DIFFSERV table. The DIFFSERV table is not initialized upon reset on power-up. If DIFFSERV is enabled, the full table should be initialized by the host.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.14 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) Register #: 1813h Size: 32 bits This register is used to read the DIFFSERV table. BITS DESCRIPTION TYPE DEFAULT 31:3 RESERVED RO - 2:0 DIFFSERV Priority These bits specify the assigned receive priority for IP packets with a ToS/CS field that matches this index. RO 000b SMSC LAN9311/LAN9311i 383 DATASHEET Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.15 Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS) Register #: 1814h Size: 32 bits This register indicates the current DIFFSERV command status. BITS 31:1 0 DESCRIPTION TYPE DEFAULT RESERVED RO - Operation Pending When set, this bit indicates that the read or write command is taking place. This bit is cleared once the command has finished. RO SC 0b Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.16 Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG) Register #: 1840h Size: 32 bits This register is used to configure the global ingress rules. BITS TYPE DEFAULT RESERVED RO - Allow Snoop Echo When set, snooped packets are allowed to be echoed back to the source port. When cleared, snooped packets, like other packets, are never sent back to the source port.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 1 VL Higher Priority When this bit is set and VLANs are enabled, the priority from the VLAN tag has higher priority than the IP TOS/SC field. R/W 1b 0 VLAN Enable When set, VLAN ingress rules are enabled. This also enables the VLAN to be used as the transmit priority queue selection. R/W 0b Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.17 Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG) Register #: 1841h Size: 32 bits This register is used to configure the per port ingress rules.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.18 Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN) Register #: 1842h Size: 32 bits This register is used to configure the per port ingress rule for allowing only VLAN tagged packets. BITS DESCRIPTION TYPE DEFAULT 31:3 RESERVED RO - 2:0 Admit Only VLAN When set, untagged and priority tagged packets are filtered.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.19 Switch Engine Port State Register (SWE_PORT_STATE) Register #: 1843h Size: 32 bits This register is used to configure the per port spanning tree state. BITS DESCRIPTION TYPE DEFAULT 31:6 RESERVED RO - 5:4 Port State Port 2 These bits specify the spanning tree port states for Port 2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.20 Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE) Register #: 1845h Size: 32 bits This register specifies the Traffic Class table that maps the packet priority into the egress queues. BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED RO - 15:14 Priority 7 traffic Class These bits specify the egress queue that is used for packets with a priority of 7.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.21 Switch Engine Port Mirroring Register (SWE_PORT_MIRROR) Register #: 1846h Size: 32 bits This register is used to configure port mirroring. BITS 31:9 8 DESCRIPTION TYPE DEFAULT RESERVED RO - Enable RX Mirroring Filtered When set, packets that would normally have been filtered are included in the receive mirroring function and are sent only to the sniffer port.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.22 Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) Register #: 1847h Size: 32 bits This register is used to enable the special tagging mode used to determine the destination port based on the VLAN tag contents. BITS DESCRIPTION TYPE DEFAULT 31:6 RESERVED RO - 5:4 Ingress Port Type Port 2 A setting of 11b enables the usage of the VLAN tag to specify the packet destination.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.23 Switch Engine Broadcast Throttling Register (SWE_BCST_THROT) Register #: 1848h Size: 32 bits This register configures the broadcast input rate throttling. BITS 31:27 26 25:18 17 16:9 8 7:0 DESCRIPTION TYPE DEFAULT RESERVED RO - Broadcast Throttle Enable Port 2 This bit enables broadcast input rate throttling on Port 2.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.24 Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER) Register #: 1849h Size: 32 bits This register is used to allow access to a VLAN even if the ingress port is not a member. BITS DESCRIPTION TYPE DEFAULT 31:3 RESERVED RO - 2:0 Admit Non Member When set, a received packet is accepted even if the ingress port is not a member of the destination VLAN.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.25 Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG) Register #: 184Ah Size: 32 bits This register, along with the settings accessible via the Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD), is used to configure the ingress rate metering/coloring.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.26 Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD) Register #: 184Bh Size: 32 bits This register is used to indirectly read and write the ingress rate metering/color table registers. A write to this address performs the specified access.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.26.1 INGRESS RATE TABLE REGISTERS The ingress rate metering/color table consists of 24 Committed Information Rate (CIR) registers (one per port/priority), a Committed Burst Size register, and an Excess Burst Size register. All metering/color table registers are 16-bits in size and are accessed indirectly via the Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.27 Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS) Register #: 184Ch Size: 32 bits This register indicates the current ingress rate command status. BITS 31:1 0 DESCRIPTION TYPE DEFAULT RESERVED RO - Operation Pending When set, indicates that the read or write command is taking place. This bit is cleared once the command has finished. RO SC 0b Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.28 Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA) Register #: 184Dh Size: 32 bits This register is used to write the ingress rate table registers. BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED RO - 15:0 Data This is the data to be written to the ingress rate table registers as specified in the Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.29 Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA) Register #: 184Eh Size: 32 bits This register is used to read the ingress rate table registers. BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED RO - 15:0 Data This is the read data from the ingress rate table registers as specified in the Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD). Refer to Section 14.5.3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.30 Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII) Register #: 1850h Size: 32 bits This register counts the number of packets filtered at ingress on Port 0(Host MAC). This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.31 Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1) Register #: 1851h Size: 32 bits This register counts the number of packets filtered at ingress on Port 1. This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.32 Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2) Register #: 1852h Size: 32 bits This register counts the number of packets filtered at ingress on Port 2. This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.33 Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_MII) Register #: 1855h Size: 32 bits This register provides the ability to map the received VLAN priority to a regenerated priority. The regenerated priority is used in determining the output priority queue. By default, the regenerated priority is identical to the received priority.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.34 Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1) Register #: 1856h Size: 32 bits This register provides the ability to map the received VLAN priority to a regenerated priority. The regenerated priority is used in determining the output priority queue. By default, the regenerated priority is identical to the received priority.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.35 Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2) Register #: 1857h Size: 32 bits This register provides the ability to map the received VLAN priority to a regenerated priority. The regenerated priority is used in determining the output priority queue. By default, the regenerated priority is identical to the received priority.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.36 Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII) Register #: 1858h Size: 32 bits This register counts the number of MAC addresses on Port 0(Host MAC) that were not learned or were overwritten by a different address due to address table space limitations. BITS 31:0 DESCRIPTION Learn Discard This field is a count of MAC addresses not learned or overwritten and is cleared when read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.37 Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1) Register #: 1859h Size: 32 bits This register counts the number of MAC addresses on Port 1 that were not learned or were overwritten by a different address due to address table space limitations. BITS 31:0 DESCRIPTION Learn Discard This field is a count of MAC addresses not learned or overwritten and is cleared when read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.38 Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2) Register #: 185Ah Size: 32 bits This register counts the number of MAC addresses on Port 2 that were not learned or were overwritten by a different address due to address table space limitations. BITS 31:0 DESCRIPTION Learn Discard This field is a count of MAC addresses not learned or overwritten and is cleared when read.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.39 Switch Engine Interrupt Mask Register (SWE_IMR) Register #: 1880h Size: 32 bits This register contains the Switch Engine interrupt mask, which masks the interrupts in the Switch Engine Interrupt Pending Register (SWE_IPR). All Switch Engine interrupts are masked by setting the Interrupt Mask bit. Clearing this bit will unmask the interrupts.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.40 Switch Engine Interrupt Pending Register (SWE_IPR) Register #: 1881h Size: 32 bits This register contains the Switch Engine interrupt status. The status is double buffered. All interrupts in this register may be masked via the Switch Engine Interrupt Mask Register (SWE_IMR) register. Refer to Chapter 5, "System Interrupts," on page 49 for more information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS TYPE DEFAULT RC 00b Set B Valid When set, bits 14:9 are valid. RC 0b 7:4 Drop Reason A When bit 1 is set, these bits indicate the reason a packet was dropped. See the Drop Reason B description above for definitions of each value of this field. RC 0h 3:2 Source port A When bit 1 is set, these bits indicate the source port on which the packet was dropped.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4 Buffer Manager CSRs This section details the Buffer Manager (BM) registers. These registers allow configuration and monitoring of the switch buffer levels and usage. A list of the general switch CSRs and their corresponding register numbers is included in Table 14.12. 14.5.4.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.2 Buffer Manager Drop Level Register (BM_DROP_LVL) Register #: 1C01h Size: 32 bits This register configures the overall buffer usage limits. BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED RO - 15:8 Drop Level Low These bits specify the buffer limit that can be used per ingress port during times when 2 or 3 ports are active. R/W 49h R/W 64h Each buffer is 128 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.3 Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL) Register #: 1C02h Size: 32 bits This register configures the buffer usage level when a Pause frame or backpressure is sent. BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED RO - 15:8 Pause Level Low These bits specify the buffer usage level during times when 2 or 3 ports are active. R/W 21h R/W 3Ch Each buffer is 128 bytes.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.4 Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL) Register #: 1C03h Size: 32 bits This register configures the buffer usage level when a Pause frame with a pause value of 1 is sent. BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED RO - 15:8 Resume Level Low These bits specify the buffer usage level during times when 2 or 3 ports are active.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.5 Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL) Register #: 1C04h Size: 32 bits This register configures the buffer usage limits for broadcasts, multicasts, and unknown unicasts. BITS DESCRIPTION TYPE DEFAULT 31:8 RESERVED RO - 7:0 Broadcast Drop Level These bits specify the maximum number of buffers that can be used by broadcasts, multicasts, and unknown unicasts.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.6 Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII) Register #: 1C05h Size: 32 bits This register counts the number of packets dropped by the Buffer Manager that were received on Port 0(Host MAC). This count includes packets dropped due to buffer space limits and ingress rate limit discarding (Red and random Yellow dropping).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.7 Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1) Register #: 1C06h Size: 32 bits This register counts the number of packets dropped by the Buffer Manager that were received on Port 1. This count includes packets dropped due to buffer space limits and ingress rate limit discarding (Red and random Yellow dropping).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.8 Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2) Register #: 1C07h Size: 32 bits This register counts the number of packets dropped by the Buffer Manager that were received on Port 2. This count includes packets dropped due to buffer space limits and ingress rate limit discarding (Red and random Yellow dropping).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.9 Buffer Manager Reset Status Register (BM_RST_STS) Register #: 1C08h Size: 32 bits This register indicates when the Buffer Manager has been initialized by the reset process. BITS 31:1 0 DESCRIPTION TYPE DEFAULT RESERVED RO - BM Ready When set, indicates the Buffer Manager tables have finished being initialized by the reset process.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.10 Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD) Register #: 1C09h Size: 32 bits This register is used to read and write the Random Discard Weight table. A write to this address performs the specified access. This table is used to set the packet drop probability verses the buffer usage.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.11 Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA) Register #: 1C0Ah Size: 32 bits This register is used to write the Random Discard Weight table. Note: The Random Discard Weight table is not initialized upon reset or power-up. If a random discard is enabled, the full table should be initialized by the host.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.12 Buffer Manager Random Discard Table Read Data Register (BM_RNDM_DSCRD_TBL_RDATA) Register #: 1C0Bh Size: 32 bits This register is used to read the Random Discard Weight table. BITS 31:10 9:0 DESCRIPTION TYPE DEFAULT RESERVED RO - Drop Probability These bits specify the discard probability of a packet that has been colored Yellow by the ingress metering. The probability is given in 1/1024’s.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.13 Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) Register #: 1C0Ch Size: 32 bits This register is used to configure the egress VLAN tagging rules. See Section 6.5.6, "Adding, Removing, and Changing VLAN Tags," on page 79 for additional details.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 17:16 Egress Port Type Port 2 These bits set the egress port type which determines the tagging/un-tagging rules. R/W 0b RESERVED RO - 13 Insert Tag Port 1 Identical to Insert Tag Port 2 definition above. R/W 0b 12 Change VLAN ID Port 1 Identical to Change VLAN ID Port 2 definition above. R/W 0b 11 Change Priority Port 1 Identical to Change Priority Port 2 definition above.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.14 Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_00_01) Register #: 1C0Dh Size: 32 bits This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.15 Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_02_03) Register #: 1C0Eh Size: 32 bits This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.16 Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11) Register #: 1C0Fh Size: 32 bits This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.17 Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_12_13) Register #: 1C10h Size: 32 bits This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.18 Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_20_21) Register #: 1C11h Size: 32 bits This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.19 Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_22_23) Register #: 1C12h Size: 32 bits This register, along with the Buffer Manager Configuration Register (BM_CFG), is used to configure the egress rate pacing.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.20 Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII) Register #: 1C13h Size: 32 bits This register is used to specify the default VLAN ID and priority of Port 0(Host MAC). BITS DESCRIPTION TYPE DEFAULT 31:15 RESERVED RO - 14:12 Default Priority These bits specify the default priority that is used when a tag is inserted or changed on egress.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.21 Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1) Register #: 1C14h Size: 32 bits This register is used to specify the default VLAN ID and priority of Port 1. BITS DESCRIPTION TYPE DEFAULT 31:15 RESERVED RO - 14:12 Default Priority These bits specify the default priority that is used when a tag is inserted or changed on egress.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.22 Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2) Register #: 1C15h Size: 32 bits This register is used to specify the default VLAN ID and priority of Port 2. BITS DESCRIPTION TYPE DEFAULT 31:15 RESERVED RO - 14:12 Default Priority These bits specify the default priority that is used when a tag is inserted or changed on egress.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.23 Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII) Register #: 1C16h Size: 32 bits This register counts the number of packets received on Port 0(Host MAC) that were dropped by the Buffer Manager due to ingress rate limit discarding (Red and random Yellow dropping).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.24 Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1) Register #: 1C17h Size: 32 bits This register counts the number of packets received on Port 1 that were dropped by the Buffer Manager due to ingress rate limit discarding (Red and random Yellow dropping).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.25 Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) Register #: 1C18h Size: 32 bits This register counts the number of packets received on Port 2 that were dropped by the Buffer Manager due to ingress rate limit discarding (Red and random Yellow dropping).
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.26 Buffer Manager Interrupt Mask Register (BM_IMR) Register #: 1C20h Size: 32 bits This register contains the Buffer Manager interrupt mask, which masks the interrupts in the Buffer Manager Interrupt Pending Register (BM_IPR). All Buffer Manager interrupts are masked by setting the Interrupt Mask bit. Clearing this bit will unmask the interrupts.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.27 Buffer Manager Interrupt Pending Register (BM_IPR) Register #: 1C21h Size: 32 bits This register contains the Buffer Manager interrupt status. The status is double buffered. All interrupts in this register may be masked via the Buffer Manager Interrupt Mask Register (BM_IMR) register. Refer to Chapter 5, "System Interrupts," on page 49 for more information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 6:3 Drop Reason A When bit 0 is set, these bits indicate the reason a packet was dropped. See the Drop Reason B description above for definitions of each value of this field. RC 0h 2:1 Source port A When bit 0 is set, these bits indicate the source port on which the packet was dropped.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 15 Operational Characteristics 15.1 Absolute Maximum Ratings* Supply Voltage (VDD33A1, VDD33A2, VDD33BIAS, VDD33IO) (Note 15.1) . . . . . . . . . . . 0V to +3.6V Positive voltage on signal pins, with respect to ground (Note 15.2) . . . . . . . . . . . . . . . . . . . . . . . . . +6V Negative voltage on signal pins, with respect to ground (Note 15.3) . . . . . . . . . . . . . . . . . . . . . . . -0.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.3 Power Consumption This section details the power consumption of the LAN9311/LAN9311i. Power consumption values are provided for both the device-only, and for the device plus the Ethernet components on ports 1 and 2. Table 15.1 Supply and Current (10BASE-T Full-Duplex) TYPICAL (@ 3.3V) MAXIMUM (@ 3.6V) UNIT Supply current at 3.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.4 DC Specifications Table 15.3 I/O Buffer Characteristics PARAMETER SYMBOL MIN Low Input Level VILI -0.3 High Input Level VIHI Negative-Going Threshold VILT 1.01 Positive-Going Threshold VIHT SchmittTrigger Hysteresis (VIHT - VILT) TYP MAX UNITS NOTES IS Type Input Buffer V 3.6 V 1.18 1.35 V Schmitt trigger 1.39 1.6 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 15.4 100BASE-TX Transceiver Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS VOS - - 5 % 1.4 nS Overshoot and Undershoot Jitter NOTES Note 15.10 Note 15.8 Measured at line side of transformer, line replaced by 100Ω (+/- 1%) resistor. Note 15.9 Offset from 16nS pulse width at 50% of pulse peak. Note 15.10 Measured differentially. Table 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.2 Reset and Configuration Strap Timing This diagram illustrates the nRST pin timing requirements and its relation to the configuration strap pins and output drive. Assertion of nRST is not a requirement. However, if used, it must be asserted for the minimum period specified. Please refer to Section 4.2, "Resets," on page 36 for additional information.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.3 Power-On Configuration Strap Valid Timing This diagram illustrates the configuration strap valid timing requirements in relation to power-on. In order for valid configuration strap values to be read at power-on, the following timing requirements must be met. VDD33IO 2.0V tcfg Configuration Straps Figure 15.3 Power-On Configuration Strap Latching Timing Table 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.4 PIO Read Cycle Timing Please refer to Section 8.5.4, "PIO Reads," on page 107 for a functional description of this mode. A[x:1], END_SEL tcycle tah tasu tcsl tcsh nCS, nRD tdoff tcsdv tdoh tdon D[15:0] Figure 15.4 PIO Read Cycle Timing Table 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.5 PIO Burst Read Cycle Timing Please refer to Section 8.5.5, "PIO Burst Reads," on page 108 for a functional description of this mode. A[x:5], END_SEL tacyc tacyc tacyc A[4:1] tah tasu tcsh nCS, nRD tcsdv tdon tadv tadv tadv tdoff tdoh D[15:0] Figure 15.5 PIO Burst Read Cycle Timing Table 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.6 RX Data FIFO Direct PIO Read Cycle Timing Please refer to Section 8.5.6, "RX Data FIFO Direct PIO Reads," on page 109 for a functional description of this mode. FIFO_SEL A[x:1], END_SEL tcycle tasu tah tcsl tcsh nCS, nRD tdoff tcsdv tdoh tdon D[15:0] Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing Table 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing Please refer to Section 8.5.7, "RX Data FIFO Direct PIO Burst Reads," on page 110 for a functional description of this mode. FIFO_SEL END_SEL tacyc tacyc tacyc A[2:1] tah tasu tcsh nCS, nRD tcsdv tdon tadv tadv tadv tdoff tdoh D[15:0] Figure 15.7 RX Data FIFO Direct PIO Burst Read Cycle Timing Table 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.8 PIO Write Cycle Timing Please refer to Section 8.5.8, "PIO Writes," on page 111 for a functional description of this mode. A[x:1], END_SEL tcycle tasu tah tcsl tcsh nCS, nWR tdsu tdh D[15:0] Figure 15.8 PIO Write Cycle Timing Table 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.9 TX Data FIFO Direct PIO Write Cycle Timing Please refer to Section 8.5.9, "TX Data FIFO Direct PIO Writes," on page 112 for a functional description of this mode. FIFO_SEL A[2:1], END_SEL tcycle tah tasu tcsl tcsh nCS, nWR tdsu tdh D[15:0] Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing Table 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.10 Microwire Timing This section specifies the Microwire EEPROM interface timing requirements. Please refer to Section 10.2.3, "Microwire EEPROM," on page 145 for a functional description of this serial interface. tcsl EECS tcshckh tckcyc tckh tckl tcklcsl EECLK tckldis tdvckh tckhdis EEDO tdsckh tdhckh EEDI tdhcsl tcshdv EEDI (VERIFY) Figure 15.10 Microwire Timing Table 15.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.6 Clock Circuit The LAN9311/LAN9311i can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 16 Package Outlines 16.1 128-VTQFP Package Outline Figure 16.1 LAN9311 128-VTQFP Package Definition Table 16.1 LAN9311 128-VTQFP Dimensions MIN NOMINAL MAX REMARKS A - - 1.20 Overall Package Height A1 0.05 - 0.15 Standoff A2 0.95 1.00 1.05 Body Thickness D/E 15.80 16.00 16.20 X/Y Span D1/E1 13.80 14.00 14.20 X/Y Plastic Body Size L 0.45 0.60 0.75 Lead Foot Length b 0.13 0.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Notes: 1. All dimensions are in millimeters unless otherwise noted. 2. 3. 4. Dimensions b & c apply to the flat section of the lead foot between 0.10 and 0.25mm from the lead tip. The base metal is exposed at the lead tip. Dimensions D1 and E1 do not include mold protrusions. Maximum allowed protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 16.2 128-XVTQFP Package Outline Figure 16.3 LAN9311/LAN9311i 128-XVTQFP Package Definition Revision 1.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 16.2 LAN9311/LAN9311i 128-XVTQFP Dimensions MIN NOMINAL MAX REMARKS A - - 1.20 Overall Package Height A1 0.05 - 0.15 Standoff A2 0.95 1.00 1.05 Body Thickness D/E 15.80 16.00 16.20 X/Y Span D1/E1 13.80 14.00 14.20 X/Y Plastic Body Size D2/E2 6.35 6.50 6.65 X/Y Exposed Pad Size L 0.45 0.60 0.75 Lead Foot Length b 0.13 0.18 0.23 Lead Width c 0.09 - 0.
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 17 Revision History Table 17.1 Customer Revision History REVISION LEVEL & DATE Rev. 1.3 (07-03-08) Revision 1.