LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface PRODUCT FEATURES Datasheet Highlights Optimized for embedded applications with 32-bit RISC CPUs Integrated descriptor based scatter-gather DMA and IRQ deassertion timer effectively increase network throughput and reduce CPU loading Integrated Ethernet MAC with full-duplex support Integrated 10/100 Ethernet PHY with HP Auto-MDIX support 32-bit, 33MHz, PCI 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet ORDER NUMBERS: LAN9420-NU FOR 128-PIN VTQFP, LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO 70oC) LAN9420i-NU FOR 128-PIN VTQFP, LEAD-FREE ROHS COMPLIANT PACKAGE (-40o TO 85oC) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table of Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.5 3.6 3.4.2 Data Descriptors and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4.2.1 Receive Descriptors ....................................................................................................... 41 3.4.2.2 Transmit descriptors....................................................................................................... 45 3.4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.7 3.6.6 Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.6.6.1 Re-starting Auto-negotiation .......................................................................................... 71 3.6.6.2 Disabling Auto-negotiation ............................................................................................. 71 3.6.6.3 Half vs.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4 4.5 4.6 4.3.2 Transmit Poll Demand Register (TX_POLL_DEMAND) . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Receive Poll Demand Register (RX_POLL_DEMAND). . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 Receive List Base Address Register (RX_BASE_ADDR) . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 Transmit List Base Address Register (TX_BASE_ADDR). . . . . . . . . . . . . . . . . . . . . . . 4.3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.7 5.8 5.9 PCI I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet List of Figures Figure 1.1 Figure 1.2 Figure 2.1 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 3.15 Figure 3.16 Figure 3.17 Figure 3.18 Figure 3.19 Figure 3.20 Figure 3.21 Figure 3.22 Figure 3.23 Figure 3.24 Figure 3.25 Figure 3.26 Figure 3.27 Figure 3.28 Figure 3.29 Figure 4.1 Figure 4.2 Figure 5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet List of Tables Table 2.1 PCI Bus Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 2.3 GPIO and LED Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 5.13 LAN9420/LAN9420i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 6.1 LAN9420/LAN9420i 128-VTQFP Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Chapter 1 Introduction 1.1 Block Diagrams EEPROM (optional) PCI Host To Ethernet LAN9420/LAN9420i Magnetics GPIOs/LEDs (optional) PCI Bus External 25MHz Crystal PCI Device PCI Device Figure 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 1.2 General Description LAN9420/LAN9420i is a full-featured, Fast Ethernet controller which allows for the easy and costeffective integration of Fast Ethernet into a PCI-based system. A system configuration diagram of LAN9420/LAN9420i in a typical embedded environment can be seen in Figure 1.1, followed by an internal block diagram of LAN9420/LAN9420i in Figure 1.2.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 1.3 PCI Bridge LAN9420/LAN9420i implements a PCI Local Bus Specification Revision 3.0 compliant interface, supporting the PCI Bus Power Management Interface Specification Revision 1.1. It provides the PCI Configuration Space Control and Status registers used to configure LAN9420/LAN9420i for PCI device operation. Please refer to Section 3.2, "PCI Bridge (PCIB)," on page 23 for more information. 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 1.7.2 PLL and Power Management LAN9420/LAN9420i interfaces with a 25MHz crystal oscillator from which all internal clocks, with the exception of PCI clock, are generated. The internal clocks are all generated by the PLL and Power Management blocks. Various power savings modes exists that allow for the clocks to be shut down. These modes are defined by the power state of the PCI function. Please refer to Section 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet NC EECLK/GPO4 EECS NC EEDIO/GPO3 NC VDD33IO VSS AD0 AD1 AD2 AD3 AD4 VSS VDD18CORE VDD33IO VSS AD5 AD6 AD7 nCBE0 AD8 VDD33IO VSS AD9 AD10 AD11 AD12 AD13 VDD33IO VSS AD14 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 TOP VIEW 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 nGNT nREQ nPME VSS VDD
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 2.1 Pin List Table 2.1 PCI Bus Interface Pins NUM PINS NAME SYMBOL 1 1 PCI Clock In PCI Frame PCICLK nFRAME 32 PCI Address and Data Bus PCI Reset PCI Bus Command and Byte Enables PCI Initiator Ready PCI Target Ready PCI Stop AD[31:0] 1 4 1 PCInRST nCBE[3:0] DESCRIPTION IS IPCI/ OPCI IPCI/ OPCI IS IPCI/ OPCI PCI Clock In: 0 to 33MHz PCI Clock Input.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 2.2 EEPROM NUM PINS 1 1 1 NAME SYMBOL BUFFER TYPE EEPROM Data EEDIO IS/O8 GPO3 GPO3 O8 TX_EN TX_EN O8 TX_CLK TX_CLK O8 EEPROM Chip Select EEPROM Clock EECS O8 EECLK GPO4 GPO4 IS/O8 (PU) Note 2.1 O8 RX_DV RX_DV O8 RX_CLK RX_CLK O8 Note 2.1 SMSC LAN9420/LAN9420i DESCRIPTION EEPROM Data: This bi-directional pin can be connected to an optional serial EEPROM DIO.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 2.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 2.5 PLL and Ethernet PHY Pins NUM PINS NAME SYMBOL BUFFER TYPE Crystal Input XI ICLK Crystal Input: External 25MHz crystal input. This pin can also be driven by a single-ended clock oscillator. When this method is used, XO should be left unconnected. 1 Crystal Output XO OCLK Crystal Output: External 25MHz crystal output.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 2.6 Power and Ground Pins NUM PINS 2 1 1 1 15 NAME SYMBOL BUFFER TYPE +3.3V Analog Power Supply VDD33A P +1.8V PLL Power Supply VDD18PLL +1.8V TX Power Supply VDD18TX +3.3V Master Bias Power Supply VDD33BIAS +3.3V I/O Power VDD33IO DESCRIPTION +3.3V Analog Power Supply Refer to the LAN9420/LAN9420i application note for connection information. P +1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 2.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 2.2 Buffer Types BUFFER TYPE DESCRIPTION IS Schmitt-triggered Input O8 Output with 8mA sink and 8mA source current O12 Output with 12mA sink and 12mA source current OD12 Open-drain output with 12mA sink current IPCI PCI compliant Input OPCI PCI compliant Output PU 50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-ups are always enabled.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Chapter 3 Functional Description 3.1 Functional Overview The LAN9420/LAN9420i Ethernet Controller consists of five major functional blocks. These blocks are: PCI Bridge (PCIB) System Control Block (SCB) DMA Controller (DMAC) 10/100 Ethernet MAC 10/100 Ethernet PHY The following sections discuss the features of each block. A block diagram of LAN9420/LAN9420i is shown in Figure 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.2.1 PCI Bridge (PCIB) Block Diagram PCI Bridge (PCIB) To/From DMAC Arbiter PCI Master PCI To/From CSR Blocks PCI Target nPME nINT PM Related Signals (To/From PM) PCI Configuration Space CSR PM Signal (From PM) PME Gating IRQ (From INT) Interrupt Gating Figure 3.1 PCI Bridge Block Diagram Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.2.2 PCI Interface Environments The PCIB supports only Device operation. It functions as a simple bridge, permitting LAN9420/LAN9420i to act as a master/target PCI device on the PCI bus. The Host performs PCI arbitration and is responsible for initializing configuration space for all devices on the bus. Figure 3.2 illustrates Device operation.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.2.4 PCI Target Interface The PCI target interface implements the address spaces listed in Table 3.1. Table 3.1 PCI Address Spaces SPACE SIZE Configuration 256 bytes BAR0...
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet . BA + 3FCh CSR - Big Endian (512 Bytes) BA + 200h BA + 1FCh CSR - Little Endian (512 Bytes) BA (BAR3) Figure 3.3 CSR Double Endian Mapping 3.2.4.2.2 I/O MAPPING OF CSR The I/O BAR (BAR4) is double mapped over the CSR space with the non-prefetchable area. The CSR big endian space is disabled, as the Host processors (Intel x86) that use the I/O BAR are little endian. Note: A comparison of Figure 3.3 with Figure 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Bit 3 of the PCI Device Status Register. The PCI Device Status Register and PCI Device Command Register are standard registers in PCI Configuration Space. Please refer to Section 4.6, "PCI Configuration Space CSR (CONFIG CSR)," on page 149 for details. PCIB Interrupt Controller Bit 3 PCI Device Status Register IRQ nINT RW (To Host) Bit 10 PCI Device Command Register Figure 3.5 Interrupt Generation 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet General-purpose timer interrupt (GPT_INT) General purpose Input/Output interrupt (GPIOx_INT) Software interrupt (SW_INT) Master bus error interrupt (MBERR_INT) Slave bus error interrupt (SBERR_INT) Wake event detection (WAKE_INT) A Block diagram of the Interrupt Controller is shown in Figure 3.6 .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet write of '1' to the corresponding status bit in the INT_STS register. The remaining interrupts are cleared from the source CSR. The Interrupt Controller receives the wake event detection interrupt (WAKE_INT) from the wake detection logic.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Once enabled, the GPT counts down either until it reaches 0000h, or until a new pre-load value is written to the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT interrupt status bit (GPT_INT) and the GPT interrupt (if the GPT_INT_EN bit is set), and continues counting. GPT_INT is a sticky bit (R/WC), Once the GPT_INT bit is asserted, it can only be cleared by writing a '1' to the bit.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Note: EEPROM byte addresses past 0Ah can be used to store data for any purpose. The signature value of 0xA5 is stored at address 0. A different signature value indicates to the EEPROM controller that no EEPROM or an un-programmed EEPROM is attached to LAN9420/LAN9420i. In this case, following default values are used for the Subsystem Device ID (SSID), Subsystem Vendor ID (SSVID), and the MAC address. Table 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM, the Host must first issue the EWEN command. If an operation is attempted, and an EEPROM device does not respond within 30mS, LAN9420/LAN9420i will timeout, and the EPC Time-out bit (EPC_TO) in the E2P_CMD register will be set. Figure 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet tCSL EECS EECLK EEDIO (OUTPUT) 1 1 1 A6 A0 EEDIO (INPUT) Figure 3.8 EEPROM ERASE Cycle ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. tCSL EECS EECLK EEDIO (OUTPUT) 1 0 0 1 0 EEDIO (INPUT) Figure 3.9 EEPROM ERAL Cycle Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations issue the EWEN command. tCSL EECS EECLK EEDIO (OUTPUT) 1 0 0 0 0 EEDIO (INPUT) Figure 3.10 EEPROM EWDS Cycle EWEN (Erase/Write Enable): Enables the EEPROM for erase and write operations.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC Address (EPC_ADDR). The result of the read is available in the E2P_DATA register. tCSL EECS EECLK EEDIO (OUTPUT) 1 1 0 A6 A0 EEDIO (INPUT) D7 D0 Figure 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not respond within 30ms. tCSL EECS EECLK EEDIO (OUTPUT) 1 0 0 0 D7 1 D0 EEDIO (INPUT) Figure 3.14 EEPROM WRAL Cycle Table 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.3.6 System Control and Status Registers (SCSR) Please refer to Section 4.2, "System Control and Status Registers (SCSR)," on page 86 for a complete description of the SCSR. 3.4 DMA Controller (DMAC) The DMA Controller is designed to transfer data from and to the MAC RX and TX Data paths. Similar to the MAC, it contains separate TX and RX data paths that are controlled by a single arbiter.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Descriptor lists and data buffers, described in this chapter. The DMAC transfers RX data frames to the RX buffers in Host memory and transmits data from TX buffers in the Host memory. Descriptors that reside in Host memory contain pointers to these buffers. There are two DMA descriptor lists; one for receive operations and one for transmit operations.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Ring Structure: BUFFER 1 DESCRIPTOR 0 BUFFER 2 BUFFER 1 DESCRIPTOR 1 BUFFER 2 BUFFER 1 DESCRIPTOR n BUFFER 2 Chain Structure: BUFFER 1 DESCRIPTOR 0 BUFFER 1 DESCRIPTOR 1 NEXT DESCRIPTOR Figure 3.15 Ring and Chain Descriptor Structures Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.4.2.1 Receive Descriptors The receive descriptors must be 4-DWORD (16-byte) aligned. Except for the case where descriptor address chaining is disabled (RCH=0), there are no alignment restrictions on receive buffer addresses. Providing two buffers, two byte-count buffers, and two address pointers in each descriptor facilitates compatibility with various types of memory-management schemes. Figure 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 3.5 RDES0 Bit Fields (continued) BITS DESCRIPTION 29:16 FL - Frame Length Indicates the length in bytes, including the CRC, of the received frame that was transferred to Host memory. This field is set only after the last descriptor (LS) bit is set and the descriptor error (DE) is reset. Host Actions: Reads this field to determine Frame Length. DMAC Actions: Initializes this field to define Frame Length.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 3.5 RDES0 Bit Fields (continued) BITS DESCRIPTION 7 TL - Frame Too Long When set, indicates the frame length exceeds maximum Ethernet-specified size of 1518 bytes (or 1522 bytes when VLAN tagging is enabled). This bit is valid only when last descriptor (LS) is set. Frame too long is only a frame length indication and does not cause any frame truncation. Host Actions: Checks this bit to determine status.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Receive Descriptor 1 (RDES1) Table 3.6 RDES1 Bit Fields BITS 31:26 DESCRIPTION RESERVED Host Actions: Cleared on writes and ignored on reads. DMAC Actions: Ignored on reads. DMAC does not write to RDES1. 25 RER - Receive End of Ring When set, indicates that the DMAC reached the final descriptor.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Receive Descriptor 3 (RDES3) Table 3.8 RDES3 Bit Fields BITS DESCRIPTION 31:0 Buffer 2 Address Pointer (Next Descriptor Address) The RCH (Second Address Chained) bit (RDES1[24]) determines the usage of this field as follows: RCH is zero: This field contains the pointer to the address of buffer 2 in Host memory. The buffer must be DWORD (32-bit) aligned (RDES3[1:0] = 00b).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Transmit Descriptor 0 (TDES0) TDES0 contains the transmitted frame status and the descriptor ownership information. Table 3.9 TDES0 Bit Fields BITS 31 DESCRIPTION OWN - Own Bit When set, indicates that the descriptor block and associated buffer(s) are owned by the DMA controller. When reset, indicates that the descriptor block and associated buffer(s) are owned by the Host system.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 3.9 TDES0 Bit Fields (continued) BITS 8 DESCRIPTION EC - Excessive Collision When set, indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. Host Actions: Checks this bit to determine status. DMAC Actions: Sets/clears this bit to define status. 7 RESERVED Host Actions: Cleared on writes and ignored on reads.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 3.10 TDES1 Bit Fields (continued) BITS 28 DESCRIPTION RESERVED Host Actions: Cleared on writes and ignored on reads. DMAC Actions: Ignored on reads. DMAC does not write to TDES1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Transmit Descriptor 2 (TDES2) Table 3.11 TDES2 Bit Fields BITS DESCRIPTION 31:0 Buffer 1 Address Pointer This is the physical address of buffer 1. There are no limitations on the buffer address alignment. Host Actions: Initializes this field. DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer address. Transmit Descriptor 3 (TDES3) Table 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Note: The TX and RX processes and paths are independent of each other and can be started or stopped independently of one another. However, the control sequence required to activate the RX path must be followed explicitly. The RX DMAC should be activated before the MAC’s receiver. Failure to do so may lead to unpredictable results and untoward operation. 3.4.4 Transmit Operation Transmission proceeds as follows: 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.4.9 TX Buffer Fragmentation Rules Transmit buffers must adhere to the following rules: Each buffer can start and end on any arbitrary byte alignment The first buffer of any transmit packet can be any length Middle buffers (i.e.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.5 10/100 Ethernet MAC The Ethernet Media Access Controller (MAC) provides the following features: Compliant with the IEEE 802.3 and 802.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet retransmission and detection of collision frames, as well as an L3 checksum offload engine for transmit and receive operations. The MAC can sustain transmission or reception of minimally-sized back-to-back packets at full line speed with an inter-packet gap (IPG) of 9.6 microseconds for 10 Mbps and 0.96 microseconds for 100 Mbps.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet . Ethernet frame (1518 BYTES) PREAMBLE (7 BYTES) SOF (1 BYTE) DEST. ADDR. (6 BYTES) SOURCE ADDR. (6 BYTES) TYPE (2 BYTES) DATA (46 - 1500 BYTES) FCS (4 BYTES) Ethernet frame with VLAN TAG (1522 BYTES) PREAMBLE (7 BYTES) SOF (1 BYTE) DEST. ADDR. (6 BYTES) SOURCE ADDR.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 3.13 Address Filtering Modes (continued) MCPAS PRMS INVFILT HFILT HPFILT DESCRIPTION 1 0 0 0 X Pass all multicast frames. Frames with physical addresses are perfect-filtered 1 0 0 1 1 Pass all multicast frames. Frames with physical addresses are hashfiltered 3.5.3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.5.4 Wakeup Frame Detection Setting the Wakeup Frame Enable bit (WAKE_EN) in the “WUCSR—Wakeup Control and Status Register”, places the MAC in the wakeup frame detection mode. In this mode, normal data reception is disabled, and detection logic within the MAC examines receive data for the pre-programmed wakeup frame patterns.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether or not this is a wakeup frame. Table 3.15, describes the byte mask’s bit fields. Table 3.15 Filter i Byte Mask Bit Definitions FILTER i BYTE MASK DESCRIPTION BITS 31 30:0 DESCRIPTION RESERVED Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte pattern-offset + j of the incoming frame.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 3.18 Filter i CRC-16 Bit Definitions FILTER i CRC-16 DESCRIPTION BITS DESCRIPTION 15:0 Pattern CRC-16: This field contains the 16-bit CRC value from the pattern and the byte mask programmed to the wakeup filter register function. This value is compared against the CRC calculated on the incoming frame, and a match indicates the reception of a wakeup frame. Table 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Then the MAC inspects the frame for 16 repetitions of the MAC address without any breaks or interruptions. In case of a break in the 16 address repetitions, the MAC scans for the 48'hFF_FF_FF_FF_FF_FF pattern again in the incoming frame. The 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Example frame configurations: DST 0 p r o t SRC 1 2 L3 Packet F C S 3 Calculate Checksum Figure 3.20 Type II Ethernet Frame DST 0 SRC 1 2 8 t V 1 y I 0 p D 0 e 3 F C S L3 Packet 4 Calculate Checksum Figure 3.21 Ethernet Frame with VLAN Tag {DSAP, SSAP, CTRL, OUI[23:16]} DST 0 SRC 1 2 S L N e A n P 0 3 {OUI[15:0], PID[15:0]} S N A P 1 4 L3 Packet F C S 5 Calculate Checksum Figure 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet {DSAP, SSAP, CTRL, OUI[23:16]} DST 0 S 8 V L N 1 I e A 0 D n P 0 0 SRC 1 2 3 4 {OUI[15:0], PID[15:0]} S N A P 1 5 F C S L3 Packet 6 Calculate Checksum Figure 3.23 Ethernet Frame with VLAN Tag and SNAP Header {DSAP, SSAP, CTRL, OUI[23:16]} DST 0 SRC 1 2 S 8 8 V V L N 1 1 I I e A 0 0 D D n P 0 0 0 4 5 6 {OUI[15:0], PID[15:0]} S N A P 1 7 F C S L3 Packet 8 Calculate Checksum Figure 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.5.5.1 RX Checksum Calculation The checksum is calculated 16 bits at a time. In the case of an odd sized frame, an extra byte of zero is used to pad up to 16 bits. Consider the following packet: DA, SA, Type, B0, B1, B2 … BN, FCS Let [A, B] = A*256 + B; If the packet has an even number of octets then checksum = [B1, B0] + C0 + [B3, B2] + C1 + … + [BN, BN-1] + CN-1 Where C0, C1, ...
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 3.20 TX Checksum Preamble (continued) BITS DESCRIPTION 11:0 TXCSSP - TX Checksum Start Pointer This field indicates start offset, in bytes, where the checksum calculation will begin in the associated TX packet. Note: 3.5.6.1 The data checksum calculation must not begin in the MAC header (first 14 bytes) or in the last 4 bytes of the TX packet.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 100M PLL TX_CLK MAC Internal MII 25 MHz by 4 bits 25MHz by 4 bits MII 4B/5B Encoder 25MHz by 5 bits Scrambler and PISO MLT-3 Magnetics 125 Mbps Serial NRZI Converter MLT-3 Converter NRZI Tx Driver MLT-3 MLT-3 RJ45 MLT-3 CAT-5 Figure 3.25 100BASE-TX Data Path 3.6.1 100BASE-TX Transmit The data path of the 100BASE-TX is shown in Figure 3.25. Each major block is explained below. 3.6.1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.6.1.3 NRZI and MLT3 Encoding The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”. 3.6.1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m and 150m. If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the isolation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW) on the received signal will result.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.6.3 10BASE-T Transmit Data to be transmitted comes from the MAC. The 10BASE-T transmitter receives 4-bit nibbles from the internal MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. The 10M transmitter uses the following blocks: 3.6.3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet is indicated by the flag “XPOL“, bit 4 in register 27. The 10M PLL is locked onto the received Manchester signal and from this, generates the received 20MHz clock. Using this clock, the Manchester encoded data is extracted and converted to a 10MHz NRZI data stream. It is then converted from serial to 4-bit wide parallel data.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE 802.3 clause 28. In summary, the PHY advertises 802.3 compliance in its selector field (the first 5 bits of the Link Code Word). It advertises its technology ability according to the bits set in register 4 of the SMI registers. There are 4 possible matches of the technology abilities.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.6.6.3 Half vs. Full-Duplex Half-duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity. In this mode, If data is received while the PHY is transmitting, a collision results.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Note: For maximum power savings, auto-negotiation should be disabled before enabling the General Power-Down mode. 3.6.8.2 Energy Detect Power-Down This power-down mode is activated by setting the PHY register bit 17.13 to 1. Please refer to Section 4.5.8, "Mode Control/Status," on page 143 for additional information on this register.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet the nPME signal upon detection of various power management events, such as an Ethernet “Wake On LAN”, or upon detection of an Ethernet link status change. As a result of the nPME assertion by the device, the PCI Host can reconfigure the power management state.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.7.3 Device Clocking LAN9420/LAN9420i requires a fixed-frequency 25MHz clock source. This is typically provided by attaching a 25MHz crystal to the XI and XO pins. The clock can optionally be provided by driving the XI input pin with a single-ended 25MHz clock source. If a single-ended source is selected, the clock input must run continuously for normal device operation.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.7.4.1.2 EXITING THE G3 STATE When the system leaves the G3 state, the device will behave as follows. State transitions are illustrated in Figure 3.28 on page 75. 3.7.4.2 G3 to D3COLD (T6): This transition occurs when VAUXDET is connected to the PCI 3.3Vaux power supply and all power is off (PCInRST=X, PM_STATE=X, VAUXDET=0, PWRGOOD=0) and then 3.3Vaux is applied (PCInRST=0, PM_STATE=X, VAUXDET=0 to 1, PWRGOOD=0).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet detection. Refer to section Section 3.7.6, "Detecting Power Management Events," on page 80 for more information. 3.7.4.3.2 EXITING THE D0A STATE The device will exit the D0A state under the following conditions. State transitions are illustrated in Figure 3.28 on page 75. 3.7.4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.7.4.5 D3HOT to D0U (T8): This transition occurs when PCInRST is asserted while in the D3HOT state (PCInRST=1 to 0, PM_STATE=11b, VAUXDET=X, PWRGOOD=1). Refer to Section 3.7.5, "Resets," on page 79 to for more information on this reset. D3HOT to G3 (T12): This transition occurs when all power supplies are turned off (PCInRST=X, PM_STATE=XXb, VAUXDET=1 to 0, PWRGOOD=1 to 0). For example, total power failure.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 3.7.5 Resets The LAN9420/LAN9420i device employs the following resets: Power-On Reset (POR): This reset is asserted on initial application of device power. If the device is powered from the PCI auxiliary power supply, this reset is asserted for approximately 21mS after 3.3Vaux has reached its operational level.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Note 3.10 PHY register bits designated as NASR are not initialized by setting the PHY Soft Reset bit in the PHY’s Basic Control Register. Note 3.11 PHY reset conditions and mode settings are discussed in Section 3.7.5.1, "PHY Resets," on page 80 3.7.5.1 PHY Resets In addition to the PHY_RST, PHY_SRST and PCInRST noted in Table 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Two control bits are implemented in the PMT_CTRL SCSR: Wake-on-LAN enable (WOL_EN) and Energy Detect enable (ED_EN). Depending on the state of these control bits, the logic will generate an internal wake event interrupt when the MAC detects a wakeup event (Wakeup Frame or Magic Packet), or a PHY interrupt is asserted (energy detect). Two Wakeup Status (WUPS) are implemented in the SCSR space.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet b. The software application must wait for all pending DMA transactions to complete. Upon completion, no further transactions are permitted. 2. The ENERGYON event must be enabled as a PHY interrupt source. This is done by setting the INT7 bit in the PHY’s Interrupt Source Flag register. 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Chapter 4 Register Descriptions The registers are partitioned into five groups. The first group is the System Control and Status Registers (SCSR). The second group is the DMA Control and Status Registers (DCSR). These registers are located within the DMAC and are used to control DMA-specific functions. The third group is the MAC Control and Status Registers (MCSR).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet N o te : B A R 3 – M e m S p a c e is 1 K B B A R 4 – I/O S p a c e is 2 5 6 B BA + 1FCh RESERVED (D O N O T U S E ) BA + 100h BA + 0FCh BA + C0h S y s te m C o n tro l a n d S ta tu s R e g is te rs (S C S R 's ) BA + BCh RESERVED (D O N O T U S E ) BA + B4h BA + B0h BA + 80h MAC C o n tro l a n d S ta tu s R e g is te rs (M C S R 's ) BA + 7Ch RESERVED (D O N O T U S E ) BA + 58h BA + 54h BA DMAC C o n tro
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.1 Register Nomenclature Table 4.1 describes the register bit attributes used throughout this section. Table 4.1 Register Bit Types REGISTER BIT TYPE NOTATION REGISTER BIT DESCRIPTION R Read: A register or bit with this attribute can be read. W Write: A register or bit with this attribute can be written. RO Read only: Read only. Writes have no effect.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2 System Control and Status Registers (SCSR) Table 4.2, "System Control and Status Register Addresses" lists the registers contained in this section. Table 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.1 ID and Revision (ID_REV) Offset: 00C0h Size: 32 bits This register contains the device ID and block revision. BITS DESCRIPTION TYPE DEFAULT 31:16 Chip ID. This 16-bit field is used to identify the device model. RO 9420h 15:0 Block Revision. This 16-bit field is used to identify the revision of the Ethernet Subsystem. RO Note 4.1 Note 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.2 Interrupt Control Register (INT_CTL) Offset: 00C4h Size: 32 bits Interrupts are enabled/disabled through this register. Refer to Section 3.3.1, "Interrupt Controller," on page 28 for more information on the Interrupt Controller. Note: The DMAC interrupt (DMAC_INT) is enabled through the DCSR.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.3 Interrupt Status Register (INT_STS) Offset: 00C8h Size: 32 bits This register contains the current status of the generated interrupts. Some of these interrupts are also cleared through this register. BITS 31:16 DESCRIPTION RESERVED 15 Software Interrupt (SW_INT) This bit latches high upon the SW_INT_EN bit toggling from a 0 to 1. The interrupt is cleared by writing a ‘1’. Writing ‘0’ has no effect.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 1 Wake Event Interrupt (WAKE_INT) Indicates a valid MAC wakeup event (Wakeup Frame or Magic Packet) or PHY interrupt (Energy-Detect) has been received. The particular source of the interrupt can be determined by the WUPS field of the Power Management Control Register (PMT_CTRL). Both WUPS bits must be cleared in order to clear WAKE_INT. Writing to the WAKE_INT bit has no effect.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.4 Interrupt Configuration Register (INT_CFG) Offset: 00CCh Size: 32 bits This register configures and monitors the interrupt (IRQ) signal. Control of the de-assertion interval for the IRQ is also included. The de-assertion interval is the minimum time the IRQ will remain de-asserted after it has been asserted and cleared. After this time period has elapsed, the IRQ will be asserted if the interrupt is active.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.5 General Purpose Input/Output Configuration Register (GPIO_CFG) Offset: 00D0h Size: 32 bits This register configures the GPIO and LED functions. BITS 31 30:28 DESCRIPTION TYPE DEFAULT RESERVED RO - LED[3:1] enable (LEDx_EN) A ’1’ sets the associated pin as an LED output. When cleared low, the pin functions as a GPIO signal.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 10:8 GPIO Direction 0-2 (GPDIRn) When set, enables the corresponding GPIO as an output. When cleared the GPIO is enabled as an input. Bits are assigned as follows: R/W 000b GPIO0 – bit 8 GPIO1 – bit 9 GPIO2 – bit 10 7:5 RESERVED RO - 4:3 GPO Data 3-4 (GPODn) The value written is reflected on GPOn. Bits are assigned as follows: R/W 00b R/W Note 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.6 General Purpose Timer Configuration Register (GPT_CFG) Offset: 00D4h Size: 32 bits This register configures the general purpose timer (GPT). The GPT can be configured to generate interrupts at intervals defined in this register. Refer to Section 3.3.3, "General Purpose Timer (GPT)," on page 30 for more information on the General Purpose Timer.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.7 General Purpose Timer Current Count Register (GPT_CNT) Offset: 00D8h Size: 32 bits This register reflects the current value of the general purpose timer. BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED RO - 15:0 General Purpose Timer Current Count (GPT_CNT) This 16-bit field reflects the current value of the GPT. RO FFFFh SMSC LAN9420/LAN9420i 95 DATASHEET Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.8 Bus Master Bridge Configuration Register (BUS_CFG) Offset: 00DCh Size: 32 bits This register determines the bus arbitration characteristics for the RX and TX DMA engines. BITS DESCRIPTION TYPE DEFAULT 31:28 RESERVED RO - 27 RESERVED R/W 0b RX/TX Arbitration Priority Select (CSR_RXTXWEIGHT) This field selects the arbitration priority ratio for receive and transmit DMA operations.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.9 Power Management Control Register (PMT_CTRL) Offset: 00E0h Size: 32 bits This register controls the wake event detection features. This register also controls the SCSR soft reset to the PHY. Note: If waking from a reduced-power state causes the assertion of a device reset, this register will be cleared. BITS TYPE DEFAULT RESERVED RO - 10 PHY Reset (PHY_RST) Writing a ‘1’ to this bit resets the PHY.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.10 Free Run Counter (FREE_RUN) Offset: 00F4h Size: 32 bits This register reflects the value of the free-running (6.25Mhz) counter (FRC). BITS DESCRIPTION TYPE DEFAULT 31:0 Free Running Counter (FR_CNT) This field reflects the value of a free-running 32-bit counter. At reset, the counter starts at zero and is incremented for every 160ns cycle. When the maximum count has been reached the counter will rollover.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.11 EEPROM Command Register (E2P_CMD) Offset: 00F8h Size: 32 bits This register is used to control the read and write operations with the serial EEPROM. BITS DESCRIPTION TYPE DEFAULT 31 EPC Busy (EPC_BSY) When a 1 is written into this bit, the operation specified in the EPC command field is performed at the specified EEPROM address. This bit will remain set until the operation is complete.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 30-28 EPC Command (EPC_CMD) This field is used to issue commands to the EEPROM controller. The EPC will execute commands when the EPC Busy bit is set. A new command must not be issued until the previous command completes.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 8 EEPROM Loaded When set, this bit indicates that a valid EEPROM was found, and that the MAC address and SSVID/SSID programming have completed normally. This bit is set after a successful load of the MAC address and SSVID/SSID after power-up, or after a RELOAD command has completed.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.2.12 EEPROM Data Register (E2P_DATA) Offset: 00FCh Size: 32 bits This register is used in conjunction with the E2P_CMD register to perform read and write operations with the serial EEPROM. BITS DESCRIPTION TYPE DEFAULT 31:8 RESERVED RO - 7:0 EEPROM Data Value read from or written to the EEPROM. R/W Note 4.3 Note 4.3 Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3 DMAC Control and Status Registers (DCSR) Table 4.4 lists the registers contained in this section. Table 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.1 Bus Mode Register (BUS_MODE) Offset: 0000h Size: 32 bits This register establishes the bus operating modes for the DMAC. BITS DESCRIPTION TYPE DEFAULT 31:14 RESERVED RO - 13:8 Programmable Burst Length (PBL) Indicates the maximum number of DWORDs to be transferred in one DMA transaction. This will be the maximum value that is used in a single block read/write.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.2 Transmit Poll Demand Register (TX_POLL_DEMAND) Offset: 0004h Size: 32 bits This register enables the TX DMA engine to check for new descriptors. BITS DESCRIPTION TYPE DEFAULT 31:0 Transmit Poll Demand (TPD) When written with any value, the DMAC will check for frames to be transmitted.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.3 Receive Poll Demand Register (RX_POLL_DEMAND) Offset: 0008h Size: 32 bits This register enables the RX DMAC to check for new descriptors. BITS DESCRIPTION TYPE DEFAULT 31:0 Receive Poll Demand (RPD) When written with any value, the DMAC will check for receive descriptors.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.4 Receive List Base Address Register (RX_BASE_ADDR) Offset: 000Ch Size: 32 bits This register specifies the start address of the receive buffer list. RX_BASE_ADDR must be 4-DWORD (16 byte) aligned (e.g. Reserved address bits 3:0 must be 0). BITS DESCRIPTION TYPE DEFAULT 31:4 Start of Receive List (SRL) This field points to the start of the receive buffer descriptor list.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.5 Transmit List Base Address Register (TX_BASE_ADDR) Offset: 0010h Size: 32 bits This register specifies the start address of the transmit buffer list. TX_BASE_ADDR must be 4-DWORD (16 byte) aligned (e.g. Reserved address bits 3:0 must be 0). BITS DESCRIPTION TYPE DEFAULT 31:4 Start of Transmit List (STL) This field points to the start of the transmit buffer descriptor list.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.6 DMA Controller Status Register (DMAC_STATUS) Offset: 0014h Size: 32 bits This register contains all of the status bits that the DMAC reports to the Host system. Most of the fields in this register will cause an interrupt. Status can be checked as part of an interrupt service routine, or by polling. DMAC interrupts can be masked in the DMAC_INTR_ENA register.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS 14:10 DESCRIPTION RESERVED TYPE DEFAULT RO - 9 Receive Watchdog Timeout (RWT) A Receive Watchdog Timeout occurs when the length of the receiving frame is greater than 2048 bytes through 2560 bytes. R/WC 0b 8 Receive Process Stopped (RPS) Asserted when the Receive process enters the stopped state.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.7 DMA Controller Control (Operation Mode) Register (DMAC_CONTROL) Offset: 0018h Size: 32 bits This register establishes the RX and TX operating modes and commands. This should be the last DCSR written as part of initialization. BITS DESCRIPTION TYPE DEFAULT 31:23 RESERVED RO - 22 RESERVED R/W 0b 21 Must Be One (MBO) This bit must be set to ‘1’ for normal device operation.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 1 Start/Stop Receive (SR) When set, the Receive Process is placed in the Running state. The DMA Controller attempts to acquire the descriptor from the receive list and process incoming frames.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.8 DMA Controller Interrupt Enable Register (DMAC_INTR_ENA) Offset: 001Ch Size: 32 bits This register enables the DMAC interrupts reported in the DMAC_STATUS register. Setting a bit to 1 enables the corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 1 Transmit Process Stopped (TPS_EN) The Transmit Process Stopped Interrupt is enabled only when this bit and the Abnormal Interrupt Summary Enable bit (bit [15]) are set. R/W 0b 0 Transmit Interrupt (TI_EN) The Transmit Interrupt is enabled only when this bit and the Normal Interrupt Summary Enable bit (bit [16]) are set. R/W 0b Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.9 Missed Frame and Buffer Overflow Counter Reg (MISS_FRAME_CNTR) Offset: 0020h Size: 32 bits The DMAC maintains two counters to track the number of missed frames during a receive operation. The MISS_FRAME_CNTR register reports the current value of these counters and their overflow bits. BITS TYPE DEFAULT RESERVED RO - MIL RX FIFO Full Counter Overflow (MIL_OVER) Overflow bit for the MIL_FIFO_FULL counter.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.10 Current Transmit Buffer Address Register (TX_BUFF_ADDR) Offset: 0050h Size: 32 bits This register points to the current transmit buffer address being read by the DMAC. BITS DESCRIPTION TYPE DEFAULT 31:0 TX_BUFF_ADDR This field contains the pointer to the current buffer address pointer used by the DMAC during TX operation. RO 32‘h0 Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.3.11 Current Receive Buffer Address Register (RX_BUFF_ADDR) Offset: 0054h Size: 32 bits This register points to the current receive buffer address being read by the DMAC. BITS DESCRIPTION TYPE DEFAULT 31:0 RX_BUFF_ADDR This field contains the pointer to the current buffer address pointer used by the DMAC during RX operation. RO 32‘h0 SMSC LAN9420/LAN9420i 117 DATASHEET Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4 MAC Control and Status Registers (MCSR) Table 4.5 lists the registers contained in this section. Table 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.1 MAC Control Register (MAC_CR) Offset: 0080h Size: 32 bits This register establishes the RX and TX operating modes and includes controls for address filtering and packet filtering. BITS DESCRIPTION TYPE DEFAULT 31 Receive All Mode (RXALL) When set, all incoming packets will be received and passed on to the address filtering function for processing of the selected filtering mode on the received frame.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 15 Hash Only Filtering mode (HO) When set, the address check Function operates in the imperfect address filtering mode both for physical and multicast addresses R/W 0b 14 RESERVED RO - 13 Hash/Perfect Filtering Mode (HPFILT) When reset (0), LAN9420/LAN9420i will implement a perfect address filter on incoming frames according the address specified in the MAC address register.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 7-6 BackOff Limit (BOLMT) The BOLMT bits allow the user to set its back-off limit in a relaxed or aggressive mode. According to IEEE 802.3, the MAC has to wait for a random number [r] of slot-times (Note 4.4) after it detects a collision, where: (eq.1)0 < r < 2K The exponent K is dependent on how many times the current frame to be transmitted has been retried, as follows: (eq.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 2 Receiver Enable (RXEN) When set (1), the MAC’s receiver is enabled and will receive frames from the internal PHY. When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.2 MAC Address High Register (ADDRH) Offset: 0084h Size: 32 bits This register contains the upper 16 bits of the physical address of the MAC, where ADDRH[15:8] is the 6th octet of the RX frame. BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED RO - 15-0 Physical Address [47:32] This field contains the upper 16 bits (47:32) of the physical address of the LAN9420/LAN9420i device.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.3 MAC Address Low Register (ADDRL) Offset: 0088h Size: 32 bits This register contains the lower 32 bits of the physical address of the MAC, where ADDRL[7:0] is the first octet of the Ethernet frame. BITS DESCRIPTION TYPE DEFAULT 31:0 Physical Address [31:0] This field contains the lower 32 bits (32:0) of the Physical Address of this MAC device. R/W 32‘hF Table 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.4 Multicast Hash Table High Register (HASHH) Offset: 008Ch Size: 32 bits The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the Hash table. The most significant bit determines the register to be used (Hi/Low), while the other five bits determine the bit within the register.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.5 Multicast Hash Table Low Register (HASHL) Offset: 0090h Size: 32 bits This register defines the lower 32-bits of the Multicast Hash Table. Please refer to Section 4.4.4, "Multicast Hash Table High Register (HASHH)," on page 125 for further details. BITS 31-0 DESCRIPTION Lower 32 bits of the 64-bit Hash Table Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.6 MII Access Register (MII_ACCESS) Offset: 0094h Size: 32 bits This register is used to control the management cycles to the internal PHY. BITS DESCRIPTION TYPE DEFAULT 31-16 RESERVED RO - 15-11 PHY Address For every access to this register, this field must be set to 00001b. R/W 00000b 10-6 MII Register Index (MIIRINDA) These bits select the desired MII register in the PHY.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.7 MII Data Register (MII_DATA) Offset: 0098h Size: 32 bits This register contains either the data to be written to the PHY register specified in the MII Access Register, or the read data from the PHY register whose index is specified in the MII Access Register. Refer toSection 4.4.6, "MII Access Register (MII_ACCESS)," on page 127 for further details.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.8 Flow Control Register (FLOW) Offset: 009Ch Size: 32 bits This register is used to control the generation and reception of the Control frames by the MAC’s flow control block. A write to this register with busy bit set to 1 will trigger the Flow control block to generate a Control frame. Before writing to this register, the application has to make sure that the busy bit is not set.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.9 VLAN1 Tag Register (VLAN1) Offset: 00A0h Size: 32 bits This register contains the VLAN tag field to identify VLAN1 frames. For VLAN frames the legal frame length is increased from 1518 bytes to 1522 bytes. The RXCOE also uses this register to determine the protocol value to use to indicate the existence of a VLAN tag. When using the RXCOE, this value may only be changed if the RX path is disabled.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.10 VLAN2 Tag Register (VLAN2) Offset: 00A4h Size: 32 bits This register contains the VLAN tag field to identify VLAN2 frames. For VLAN frames the legal frame length is increased from 1518 bytes to 1522 bytes. BITS DESCRIPTION TYPE DEFAULT 31:16 RESERVED RO - 15:0 VLAN2 Tag Identifier (VTI2) This contains the VLAN Tag field to identify the VLAN2 frames.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.11 Wakeup Frame Filter (WUFF) Offset: 00A8h Size: 32 bits This register is used to configure the Wakeup Frame Filter. BITS DESCRIPTION TYPE DEFAULT 31:0 Wakeup Frame Filter (WFF) The Wakeup Frame Filter is configured through this register using an indexing mechanism. Following a reset, the MAC loads the first value written to this location to the first DWORD in the Wakeup Frame Filter (filter 0 byte mask).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.12 Wakeup Control and Status Register (WUCSR) Offset: 00ACh Size: 32 bits This register contains data pertaining to the MAC’s remote wakeup status and capabilities. BITS 31:10 9 8:7 DESCRIPTION RESERVED TYPE DEFAULT RO - Global Unicast Enable (GUE) When set, the MAC wakes up from power-saving mode on receipt of a global unicast frame. A global unicast frame has the MAC Address [0] bit set to 0.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.4.13Checksum Offload Engine Control Register (COE_CR) Offset: 00B0h Size: 32 bits This register controls the RX and TX checksum offload engines. BITS 31:17 16 DESCRIPTION TYPE DEFAULT RESERVED RO - TX Checksum Offload Engine Enable (TX_COE_EN) The COE_EN may only be changed if the TX path is disabled.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5 PHY Registers The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII_ACCESS and MII_DATA registers. An index is used to access individual PHY registers. PHY Register Indexes are shown in Table 4.7, "PHY Control and Status Registers" below.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.1 Basic Control Register Index (In Decimal): 0 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15 PHY Soft Reset 1 = PHY software reset. Bit is self-clearing. When setting this bit do not set other bits in this register. R/W/SC 0b 14 Loopback 1 = loopback mode, 0 = normal operation R/W 0b 13 Speed Select 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is enabled (0.12 = 1).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.2 Basic Status Register Index (In Decimal): BITS 1 Size: 16 bits DESCRIPTION TYPE DEFAULT 15 100BASE-T4 1 = T4 able, 0 = no T4 ability RO 0b 14 100BASE-TX Full Duplex 1 = TX with full duplex, 0 = no TX full duplex ability. RO 1b 13 100BASE-TX Half Duplex 1 = TX with half duplex, 0 = no TX half duplex ability.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.3 PHY Identifier 1 Index (In Decimal): BITS 15:0 2 Size: 16 bits DESCRIPTION PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.4 PHY Identifier 2 Index (In Decimal): BITS 15:10 3 Size: DESCRIPTION 16 bits TYPE PHY ID Number b Assigned to the 19th through 24th bits of the OUI. R/W 9:4 Model Number Six-bit manufacturer’s model number. R/W 3:0 Revision Number Four-bit manufacturer’s revision number. R/W SMSC LAN9420/LAN9420i 139 DATASHEET DEFAULT C0C3h Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.5 Auto Negotiation Advertisement Index (In Decimal): BITS 4 Size: 16 bits DESCRIPTION TYPE DEFAULT 15 RESERVED R/W 0b 14 RESERVED RO - 13 Remote Fault 1 = remote fault detected, 0 = no remote fault R/W 0b 12 RESERVED R/W - Pause Operation (See Note 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.6 Auto Negotiation Link Partner Ability Index (In Decimal): BITS 5 Size: 16 bits DESCRIPTION TYPE DEFAULT 15 Next Page 1 = next page capable, 0 = no next page ability. This device does not support next page ability.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.8 Mode Control/Status Index (In Decimal): BITS 17 Size: 16 bits TYPE DEFAULT RESERVED RO - EDPWRDOWN Enable the Energy Detect Power-Down mode: 0=Energy Detect Power-Down is disabled 1=Energy Detect Power-Down is enabled R/W 0b RESERVED RO - 1 ENERGYON Indicates whether energy is detected. This bit goes to a “0” if no valid energy is detected within 256ms.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.9 Special Modes Index (In Decimal): BITS 18 Size: 16 bits DESCRIPTION TYPE DEFAULT RO - 15:8 RESERVED 7-5 MODE PHY Mode of operation. Refer to Table 4.8 for more details. R/W NASR 111b 4-0 PHYADD PHY Address. The PHY Address is used for the SMI address. R/W NASR 00001b Table 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.10 Special Control/Status Indications Index (In Decimal): 27 Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15 Override AUTOMDIX_EN Strap 0 = AUTOMDIX_EN configuration strap enables or disables HP Auto MDIX. 1 = Override AUTOMDIX_EN configuration strap. PHY Register 27.14 and 27.13 determine MDIX function. R/W 0b 14 Auto-MDIX Enable Only effective when 27.15=1, otherwise ignored. 0 = Disable Auto-MDIX. 27.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.12 Interrupt Mask Index (In Decimal): BITS 30 Size: DESCRIPTION 16 bits TYPE DEFAULT 15:8 RESERVED RO - 7:0 Mask Bits 1 = interrupt source is enabled, 0 = interrupt source is masked R/W 00h SMSC LAN9420/LAN9420i 147 DATASHEET Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.5.13 PHY Special Control/Status Index (In Decimal): BITS 15:13 12 11:5 31 Size: 16 bits DESCRIPTION TYPE DEFAULT RESERVED RO - Autodone Auto-negotiation done indication: 0 = Auto-negotiation is not done or disabled (or not active) 1 = Auto-negotiation is done RO 0 Note 4.6 - RESERVED Write as 0000010b, ignore on read.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.6 PCI Configuration Space CSR (CONFIG CSR) Configuration and read back of the CONFIG CSR is accomplished by the Host processor via the PCI bus. These registers assume their default value on assertion of a chip-level reset or when the device power state transitions from D3 to D0. See Section 3.7, "Power Management," on page 73 for details.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 4.10 lists the standard PCI header registers that are supported. Registers whose initial values for Subsystem Vendor ID and Subsystem Device ID, are configured from the EEPROM are indicated by ‘YES’ in the “EPROM CONFIGURABLE” column. Table 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.6.1 PCI Power Management Capabilities Register (PCI_PMC) Offset: 78h Size: 32 bits This register implements the standard capability structure used to define power management features in a PCI device. The capabilities structure is documented in the PCI Bus Power Management Interface Specification Revision 1.1. The host uses this register check supported power states and features.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS DESCRIPTION TYPE DEFAULT 18:16 Power Management Specification Version (VERSION[2:0]) This device complies with Revision 1.1 of the PCI Bus Power Management Interface Specification. RO 010b 15:8 Next Item Offset (NEXT_OFFSET[7:0]) There is only a single item in the capabilities list. No other list elements follow. This field will always return 0h.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 4.6.2 PCI Power Management Control and Status Register (PCI_PMCSR) Offset: 7Ch Size: 32 bits This register controls the device’s power state. Note: The format of this register is equivalent to offsets 7:4 of the Power Management Register Block Definition as described in Revision 1.1 of the PCI Bus Power Management Interface Specification.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet BITS 1:0 DESCRIPTION Power Management State (PM_STATE) This field sets the current PM state. 00b = D0 01b = RESERVED 10b = RESERVED 11b = D3 TYPE DEFAULT R/W 00b Operations that attempt to write a RESERVED setting to this field will complete normally on the PCI bus; however D[1:0] are ignored and no state change occurs. Note 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Chapter 5 Operational Characteristics 5.1 Absolute Maximum Ratings* Supply Voltage (VDD33A, VDD33BIAS, VDD33IO) (Note 5.1) . . . . . . . . . . . . . . . . . . . . . . 0V to +3.6V Positive voltage on signal pins, with respect to ground (Note 5.2) . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Negative voltage on signal pins, with respect to ground (Note 5.3) . . . . . . . . . . . . . . . . . . . . . . . . -0.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.3 Power Consumption This section details the power consumption of LAN9420/LAN9420i as measured during various modes of operation. Power consumption values are provided for both the device-only, and for the device plus Ethernet components. Note: Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink requirements. 5.3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.3.2 D3 - Enabled for Wake Up Packet Detection Table 5.2 D3 - Enabled for Wake Up Packet Detection - Supply and Current (Typical) TYPICAL (@ 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.3.4 D3 - PHY in General Power Down Mode Table 5.4 D3 - PHY in General Power Down Mode - Supply and Current (Typical) TYPICAL (@ 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.4 DC Specifications Table 5.6 I/O Buffer Characteristics PARAMETER SYMBOL MIN Low Input Level VILI -0.3 High Input Level VIHI Negative-Going Threshold VILT 1.01 Positive-Going Threshold VIHT SchmittTrigger Hysteresis (VIHT - VILT) TYP MAX UNITS NOTES IS Type Input Buffer V 3.6 V 1.18 1.35 V Schmitt trigger 1.39 1.6 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 5.7 100BASE-TX Transceiver Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Peak Differential Output Voltage High VPPH 950 - 1050 mVpk Note 5.10 Peak Differential Output Voltage Low VPPL -950 - -1050 mVpk Note 5.10 Signal Amplitude Symmetry VSS 98 - 102 % Note 5.10 Signal Rise and Fall Time TRF 3.0 - 5.0 nS Note 5.10 Rise and Fall Symmetry TRFS - - 0.5 nS Note 5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.5 AC Specifications This section contains timing information for non-PCI signals. Note: LAN9420/LAN9420i adheres to the PCI Local Bus Specification revision 3.0. Refer to the Conventional PCI 3.0 Specification for PCI timing details and parameters. 5.5.1 Equivalent Test Load (Non-PCI Signals) Output timing specifications assume the 25pF equivalent test load illustrated in Figure 5.1 below.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.6 PCI Clock Timing The following specifies the PCI clock requirements for LAN9420/LAN9420i: PCICLK tcyc thigh tlow 0.6*VDD33IO 0.5*VDD33IO 0.4*VDD33IO p-to-p (minimum) 0.4*VDD33IO 0.3*VDD33IO 0.2*VDD33IO Figure 5.2 PCI Clock Timing Table 5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.7 PCI I/O Timing The following specifies the PCI I/O requirements for LAN9420/LAN9420i: Vth PCICLK Vtest Vtl tval PCI OUTPUTS Vtrise, Vtfall ton toff TRI-STATE PCI OUTPUTS tsu PCI INPUTS th Vth Vmax Vtest Vtl Figure 5.3 PCI I/O Timing Table 5.10 PCI I/O Timing Measurement Conditions SYMBOL VALUE UNITS Vth 0.6*VDD33IO V Vtl 0.2*VDD33IO V Vtest 0.4*VDD33IO V Vtrise 0.285*VDD33IO V Vtfall 0.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 5.11 PCI I/O Timing Values SYMBOL DESCRIPTION MIN tval PCICLK to signal valid delay - bussed signals tval(nREQ) TYP MAX UNITS 2 11 ns PCICLK to nREQ signal valid delay (Note 5.15) 2 12 ns ton Float to active delay 2 toff Active to float delay tsu Input setup time to PCICLK - bussed signals 7 ns tsu(nGNT) nGNT input setup time to PCICLK (Note 5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.8 EEPROM Timing The following specifies the EEPROM timing requirements for LAN9420/LAN9420i: tcsl EECS tcshckh tckcyc tckh tckl tcklcsl EECLK tckldis tdvckh tckhdis EEDO tdsckh tdhckh EEDI tdhcsl tcshdv EEDI (VERIFY) Figure 5.4 EEPROM Timing Table 5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet 5.9 Clock Circuit LAN9420/LAN9420i can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Chapter 6 Package Outline 6.1 128-VTQFP Package Figure 6.1 LAN9420/LAN9420i 128-VTQFP Package Definition SMSC LAN9420/LAN9420i 167 DATASHEET Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Table 6.1 LAN9420/LAN9420i 128-VTQFP Dimensions MIN NOMINAL MAX REMARKS A - - 1.20 Overall Package Height A1 0.05 - 0.15 Standoff A2 0.95 1.00 1.05 Body Thickness D/E 15.80 16.00 16.20 X/Y Span D1/E1 13.80 14.00 14.20 X/Y Plastic Body Size L 0.45 0.60 0.75 Lead Foot Length b 0.13 0.18 0.23 Lead Width c 0.09 - 0.20 Lead Foot Thickness e 0.40 BSC Lead Pitch ddd 0.00 - 0.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Chapter 7 Revision History Table 7.1 Customer Revision History REVISION LEVEL & DATE Rev. 1.22 (09-23-08) Rev. 1.21 (07-30-08) SECTION/FIGURE/ENTRY CORRECTION Added PCI SIG certification logo to cover Figure 1.2 LAN9420/LAN9420i Internal Block Diagram on page 11 Fixed error: Changed “To option..” text to “(optional)” and moved it to the end of the descriptions. Figure 1.