- Standard Microsystems Single-Chip Ethernet Controller Specification Sheet
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 29 Revision 1.22 (09-25-08)
DATASHEET
General-purpose timer interrupt (GPT_INT)
General purpose Input/Output interrupt (GPIOx_INT)
Software interrupt (SW_INT)
Master bus error interrupt (MBERR_INT)
Slave bus error interrupt (SBERR_INT)
Wake event detection (WAKE_INT)
A Block diagram of the Interrupt Controller is shown in Figure 3.6
.
The Interrupt Controller control and status register are contained within the System Control and Status
Registers (SCSR) block. The interrupt status register (INT_STS) reflects the current state of the
interrupt sources prior to qualification with their associated enables. The SW_INT, MBERR_INT,
SBERR_INT, GPIOx_INT, and GPT_INT are latched, and are cleared through the SCSR block upon a
Figure 3.6 Interrupt Controller Block Diagram
PHY Interrupt
GPIO0 Interrupt
GPIO0_INT_EN
(INT_CTL Register)
RW
GPIO0_INT
(INT_STS Register)
0 to 1
DETECT
SW_INT_EN
(INT_CTL Register)
RW
SW_INT
(INT_STS Register)
PHY_INT
(INT_STS Register)
RO
DMAC Interrupt
DMAC_INT
(INT_STS Register)
GPIO1 Interrupt
GPIO1_INT_EN
(INT_CTL Register)
RW
GPIO1_INT
(INT_STS Register)
GPIO2 Interrupt
GPIO2_INT_EN
(INT_CTL Register)
RW
GPIO2_INT
(INT_STS Register)
RO
IRQ_INT
(INT_CFG Register)
RO
DEASSERTION
TIMER
Wake Event Interrupt
WAKE_INT_EN
(INT_CTL Register)
RW
RO
WAKE_INT
(INT_STS Register)
INT_DEAS[7:0]
(INT_CFG Register)
RW RO
INT_DEAS_STS
(INT_CFG Register)
INT_DEAS_CLR
(INT_CFG Register)
RW
IRQ_EN
(INT_CTL Register)
RW
IRQ
(PCIB)
Interrupt Controller
GP Timer Interrupt
RW
GPT_INT
(INT_STS Register)
Master Bus Error
Interrupt
MBERR_INT_EN
(INT_CTL Register)
RW
Slave Bus Error
Interrupt
SBERR_INT_EN
(INT_CTL Register)
RW
MBERR_INT
(INT_STS Register)
SBERR_INT
(INT_STS Register)
GPT_INT_EN
(INT_CTL Register)
PHY_INT_EN
(INT_CTL Register)
RW