- Standard Microsystems Single-Chip Ethernet Controller Specification Sheet

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

SMSC LAN9420/LAN9420i 33 Revision 1.22 (09-25-08)

DATASHEET

Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of

the EEPROM, the Host must first issue the EWEN command.

If an operation is attempted, and an EEPROM device does not respond within 30mS,

LAN9420/LAN9420i will timeout, and the EPC Time-out bit (EPC_TO) in the E2P_CMD register will be

set.

Figure 3.7 illustrates the Host accesses required to perform an EEPROM Read or Write operation.

The Host can disable the EEPROM interface through the GPIO_CFG register. When the interface is

disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used

to monitor internal MII signals.

3.3.5.3.1 SUPPORTED EEPROM OPERATIONS

The EEPROM controller supports the following EEPROM operations under Host control via the

E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A

description and functional timing diagram is provided below for each operation. Please refer to the

E2P_CMD register description in Section 4.2.11, "EEPROM Command Register (E2P_CMD)," on

page 99 for E2P_CMD field settings for each command.

ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will

erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the

EEPROM does not respond within 30ms.

Figure 3.7 EEPROM Access Flow Diagram

Idle

Write Data

Write

Command

Read

Command

Idle

Write

Command

Read

Command

Read Data

Busy Bit = 0

EEPROM Write EEPROM Read