- Standard Microsystems Single-Chip Ethernet Controller Specification Sheet

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08) 64 SMSC LAN9420/LAN9420i
DATASHEET
3.5.6.1 TX Checksum Calculation
The TX checksum calculation is performed using the same operation as the RX checksum, with the
exception that the calculation starts as indicated by the preamble, and the transmitted checksum is the
one’s-compliment of the final calculation.
3.5.7 MAC Control and Status Registers (MCSR)
Please refer to Section 4.4, "MAC Control and Status Registers (MCSR)," on page 118 for a complete
description of the MCSR.
3.6 10/100 Ethernet PHY
LAN9420/LAN9420i integrates an IEEE 802.3 Physical Layer for Twisted Pair Ethernet applications
(PHY). The PHY can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T)
Ethernet operation.
The PHY block includes:
 Support for auto-negotiation
 Automatic polarity detection and correction
 HP Auto-MDIX
 Energy detect
 Duplex, link activity and speed indicator LEDs
 Minimal external components are required for the utilization of the integrated PHY
Functionally, the PHY can be divided into the following sections:
 100BASE-TX transmit and receive
 10BASE-T transmit and receive
 Internal MII interface to the Ethernet Media Access Controller (MAC)
 Auto-negotiation to automatically determine the best speed and duplex possible
 Management Control to read status registers and write control registers
11:0 TXCSSP - TX Checksum Start Pointer
This field indicates start offset, in bytes, where the checksum calculation will begin in the associated
TX packet.
Note: The data checksum calculation must not begin in the MAC header (first 14 bytes) or in
the last 4 bytes of the TX packet.
Table 3.20 TX Checksum Preamble (continued)
BITS DESCRIPTION