- Standard Microsystems Single-Chip Ethernet Controller Specification Sheet
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08) 72 SMSC LAN9420/LAN9420i
DATASHEET
3.6.6.3 Half vs. Full-Duplex
Half-duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect)
protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds
to both transmit and receive activity. In this mode, If data is received while the PHY is transmitting,
a collision results.
In full-duplex mode, the PHY is able to transmit and receive data simultaneously. In this mode, CRS
responds only to receive activity. The CSMA/CD protocol does not apply and collision detection is
disabled.
3.6.7 HP Auto-MDIX
HP Auto-MDIX facilitates the use of CAT-3 (10 BASE-T) or CAT-5 (100 BASE-T) media UTP
interconnect cable without consideration of interface wiring scheme. If a user plugs in either a direct
connect LAN cable, or a cross-over patch cable, as shown in Figure 3.27 on page 72, the
LAN9420/LAN9420i Auto-MDIX PHY is capable of configuring the TPO+/TPO- and TPI+/TPI- twisted
pair pins for correct transceiver operation.
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX
and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate
the symmetrical magnetics and termination of an Auto-MDIX design.
The Auto-MDIX function can be disabled through an internal register 27.15, or the external
AUTOMDIX_EN configuration strap. When Auto-MDIX mode is disabled (27.15 = 1), the TX and RX
pins can be configured as desired using the MDIX State (27.13) control bit.
3.6.8 PHY Power-Down Modes
There are 2 power-down modes for the PHY as discussed in the following sections.
3.6.8.1 General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the PHY, except the management
interface, is powered-down and stays in that condition as long as PHY register bit 0.11 is HIGH. When
bit 0.11 is cleared, the PHY powers up and is automatically reset. Please refer to Section 4.5.1, "Basic
Control Register," on page 136 for additional information on this register.
Figure 3.27 Direct Cable Connection vs. Cross-Over Cable Connection
1
2
3
4
5
6
7
8
TPO+
TPO-
TPI+
Not Used
Not Used
TPI-
Not Used
Not Used
1
2
3
4
5
6
7
8
TPO+
TPO-
TPI+
Not Used
Not Used
TPI-
Not Used
Not Used
Direct Connect Cable
RJ-45 8-pin straight-through
for 10BASE-T/100BASE-TX
signaling
1
2
3
4
5
6
7
8
TPO+
TPO-
TPI+
Not Used
Not Used
TPI-
Not Used
Not Used
1
2
3
4
5
6
7
8
TPO+
TPO-
TPI+
Not Used
Not Used
TPI-
Not Used
Not Used
Cross-Over Cable
RJ-45 8-pin cross-over for
10BASE-T/100BASE-TX
signaling