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Wearable SoC with Multi-GNSS receiver and sensor engine

CXD5602GG

Description

CXD5602GG is a 32-bit RISC low power microprocessor solution for wearable applications. It is based on the ARM

Cortex

-M4F 32-bit RISC and It integrates ARM Cortex-M0+ 32-bit RISC specifically for the system controller (power

management, clock, reset) and I/O processor. It incorporates embedded 1.5-Mbyte of SRAM, 64-Kbyte of backup SRAM,

and 256-Kbyte of I/O processor SRAM.

The ARM Cortex-M4F and ARM Cortex-M0+ are power-gated by the Power Management Unit, respectively, that is, the

CPUs are powered off by internal power switches. Processor SRAMs are able to retain data, and it’s possible to restart

processors quickly.

To provi d e o p ti miz ed h a r d wa re p er fo rm an ce f or se ns o r f u s io n and audio processing services, the device integrates ultra-low

power GNSS Domain, Audio Codec Domain and Sensor Domain. Sensor Domain provides the specialized engine for

sensor processing.

Eliminating the need for a discrete sensor hub, these features enable various sensor applications (activity recognition,

voice recognition etc.) low power audio applications such as music playback (MP3, AAC encode/decode, Bluetooth A2DP,

AVRCP etc.) and hands-free communication (Bluetooth HSP, HFP).

Features

The features of CXD5602GG are:

 Application Processor

- ARM

Cortex-M4F 32-bit RISC

- Operating frequency up to 156MHz

 1.5M-Byte Application Memory

 Application Multi-layer Bus

- 32-bit Multi-layer bus architecture

- Application Domain for ARM

Cortex-M4F 32-bit RISC, Audio Codec, Connectivity, Storage and Image

Block

 Audio Codec

- Class-D Amplifier (Digital Part)

- High Resolution audio support (up to 24-bit, 192kHz)

- Two I2S Interface support

- Unique Audio Data Format (Pulse Density Modulation) between CXD5602GG and CXD5247GF

 8-bit parallel Camera Interface support

Summary of content (52 pages)

PAGE 1
Wearable SoC with Multi-GNSS receiver and sensor engine CXD5602GG Description ® CXD5602GG is a 32-bit RISC low power microprocessor solution for wearable applications. It is based on the ARM ® Cortex -M4F 32-bit RISC and It integrates ARM Cortex-M0+ 32-bit RISC specifically for the system controller (power management, clock, reset) and I/O processor. It incorporates embedded 1.5-Mbyte of SRAM, 64-Kbyte of backup SRAM, and 256-Kbyte of I/O processor SRAM.
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CXD5602GG 2D Graphics Acceleration - BitBLT, Rotate, Scaling, Blender Connectivity/Storage Interface - On-chip USB2.0 Device support - eMMC 4.41 for eMMC Device - SD3.0 Host Controller interface - UART - SPI - Quad SPI-FLASH Interface System Control and I/O Processor (SysIOP) - ARM Cortex-M0+ 32-bit RISC - Operating frequency up to 100MHz at 1.
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CXD5602GG Multi-GNSS receiver - GPS (L1 C/A) - GLONASS (L1OF) Configurable I/O - I2C/SPI/GPIO Interfaces Debug - Serial wire debug (SWD), Embedded Trace Macrocell - UART support 3
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CXD5602GG Contents Description-------------------------------------------------------------------------------------------------------------------------------------------------- 1 Features ----------------------------------------------------------------------------------------------------------------------------------------------------- 1 Package ----------------------------------------------------------------------------------------------------------------------------------------------------- 5 Structure -
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CXD5602GG Package CXD5602GG: MFC VFBGA (FCBGA) 185pin Structure Silicon-Gate CMOS 5
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CXD5602GG Block Diagram 6
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CXD5602GG Description of Functions Application Domain Application Processor The application processor integrates six Cortex-M4s to meet the requirements of wearable devices, which demand operation in low power and performance-optimized consumer applications with the ability to scale in speed up to 156.0 MHz, the ARM Cortex-M4 Processor.
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CXD5602GG JPEG Only : up to 5M pixels Y/C Only : up to 480x360 JPEG+Y/C : 2M + WQVGA 5M + WQVGA − (JPEG High Quality mode) (JPEG Normal Quality mode) Parallel Input rate : up to 54MHz SPI Interface(SPI4) − ARM PrimeCell Synchronous Serial Port (PL022) − Communication at speeds High Performance mode: Master Half duplex mode: up to 39 Mbit/s (transmit only) Master Full duplex mode: up to 9.75 Mbit/s Low Power mode: Master Half duplex mode: up to 9.
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CXD5602GG − 8K-Byte(32bit x 512word) x2 FIFOs for Tx/Rx − Communication speeds High Performance mode: up to 39.000MHz Low Power mode: up to 24.552MHz eMMC Interface − eMMC 4.41 Protocol compatible only SDR mode − 1K-Byte(32bit x 256word) x2 FIFOs for Tx/Rx − Communication speeds High Performance mode: up to 39.000MHz Low Power mode: up to 24.
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CXD5602GG Low power mode: 128fs, 64fs of bit clock frequency Sampling rate High performance mode − Master mode : 192kHz, 96kHz, 48kHz − Slave mode: 192kHz, 96kHz, 48kHz, 44.1kHz, 16kHz, 8kHz Low power mode Master mode : 96kHz, 48kHz Slave mode: 96kHz, 48kHz, 44.
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CXD5602GG Standard-mode (100kbps) Fast-mode (400kbps) − GPIO Up to 50-bit Power Management − Clock-gating control and power gating control for components − Various low power modes are available such as Power Off, Deep Sleep, Sleep and Standby modes − Power supply voltage (VDD) for Digital and SRAM Mode: High Performance mode: VDD = 1.0V Low Power mode: VDD = 0.
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CXD5602GG PWD_SYSIOP_SUB Configurable I/O (I2C,SPI,UART) Interface SPI-FLASH Interface 128K-Byte ROM in System Control and I/O Processor Memory SYSUB-DMAC PWD_GNSS Components of GNSS Domain Excluding RF and 640K-Byte SRAM in GNSS Memory PWD_GNSS_ITP ITP Block in GNSS Domain − Digital I/O Domain: CXD5602GG has two I/O domain for digital block HOSTIF I/O Domain Others System and I/O Processor Domain System Control and I/O Processor The I/O processor integrates one Cortex-M0+ to meet the requirements of wea
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CXD5602GG AMBA® Design Kit (ADK) SP805 One channel support for each application processors System Peripherals The key features of system peripheral are: DMAC − SY-DMAC (PL081) for memory to memory transfer − SYSUB-DMAC(PL081) for SPI-FLASH Interface and Configurable I/O − S-DMAC(PL230) for Sensor Engine − H-DMAC(PL081) for Host Interface Configurable I/O (I2C,SPI,UART) Interface − SPI Interface(SPI0) PrimeCell® SSP (PL022) Master mode only, Half-duplex operation only Up to 8.
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CXD5602GG − Two dimension Infinite impulse response (IIR) filter − Norm (Fast Approximate Distance Functions): − Threshold decision for norm data Generating interrupt cause Time-stamp − Generating time-stamp based-on RTC in PMU to add to sensory data Sensory Data FIFO − 40K-Byte with 27 partitions Decimation data FIFO: 2 External sensor data FIFO: 8 Virtual sensor data FIFO: 10 Host-CPU communication buffer: 1 SPI Interface(SPI3) − PrimeCell® SSP (PL022) − Master mode only − 3 slave select
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CXD5602GG − PrimeCell® UART (PL011) − High Performance mode: Up to 3Mbps − Low Power mode: Up to 2Mbps SPI Interface(SPI2) − PrimeCell® SSP (PL022) − Slave mode only − High Performance mode: Up to 4Mbps − Low Power mode: Up to 2.7Mbps I2C Bus Interface(I2C3) − Slave mode only − Standard-mode(100 kbps) − Fast-mode(400 kbps) − Fast-mode plus (1Mbps) I2C3, SPI2 and UART0 interfaces are multiplexed, so that one interface is available at a time.
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CXD5602GG Time-To-First-Fix (TTFF) Item Remark GPS GPS & GLONASS Unit Cold Start 35 35 s Signal strength is -130 dBm Hot Start 2 2 s Test circuit as shown in the figure below GPS GPS & GLONASS Unit Remark Cold Start -147 -147 dBm Test circuit as shown in the figure below Hot Start -160 -160 dBm Tracking -161 -161 dBm Sensitivity Item Test Circuit Noise Filter An embedded noise filter for GNSS signals. It is automatically enabled at the optimum settings for the input noise.
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CXD5602GG Description of Operation Recommended operating conditions Pin Name Minimum Typical Maximum Unit 0.65 - 1.1 V LP 0.65 0.7 0.75 V HP 0.90 1.0 1.1 V DC Supply Voltage for Digital I/O 1.65 1.8 1.95 V DC Supply Voltage for Analog I/O 1.65 1.8 1.95 V VDDA_LNA DC Supply Voltage for LNA 0.65 0.7 0.75 V VDDA_LO DC Supply Voltage for LO 0.65 0.7 0.75 V DC Supply Voltage for Analog 0.65 0.7 0.75 V VDDA_XOSC DC Supply Voltage for XOSC 0.65 0.7 0.
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CXD5602GG Absolute Maximum Ratings Parameter DC Supply Voltage DC Input Voltage Power supply system Symbol Minimum Unit 0.7V VDD07 -0.3 1.05 V 1.0V VDD10 -0.3 1.5 V 1.8V VDD18 -0.3 2.5 V 3.3V(VDDA_USB33) VDD33 -0.3 4.95 V 0.7V VIN07 -0.3 1.05 V 1.8V VIN18 -0.3 2.5 V 3.3V(USB_DP/DM) VIN33 -0.3 5.
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CXD5602GG Power Consumption SysIOP Domain (including Cortex M0+) Active Power Performance − Low Power mode: VDD = 0.7V 26 uA/MHz − High Performance mode: VDD = 1.0V 51 uA/MHz Application Domain Active Power Performance − Low Power mode: VDD = 0.7V Six Cortex-M4Fs active 200 uA/MHz i.e., 34 uA/MHz,1Core One Cortex-M4F active 45 uA/MHz − High Performance mode: VDD = 1.0V Six Cortex-M4Fs active 282uA/MHz i.e.
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CXD5602GG Clocks XOSC_IN (in buffer mode) Item Symbol Min. Typ. Max. Unit Input voltage range VIN 0.8 - 1.4 Vpp Input Frequency FIN - 26.0 - MHz Input frequency characteristics FIN_C -0.5 - 0.5 ppm Duty Cycle DC 40 - 60 % Min. Typ. Max. - 32.
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CXD5602GG Electrical Characteristics DC Characteristics LVCMOS18 I/F (1.
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CXD5602GG Digital Signal AC Characteristics Serial peripheral interface (SPI) The device supports up to five serial peripheral interfaces (SPI0, SPI2, SPI3, SPI4 and SPI5). Master Mode SPIn_CS_X (Output) t CLK t LEAD t CLKWL t AG t CLKWH SPIn_SCK (Output) t OD SPIn_MOSI (Output) t SU tH SPIn_MISO (Intput) SPI0 (VDD_CORE=0.7V(LP)/1.0V(HP), VSS_DIG=0V reference, CL=30pF) Parameter Symbol Min. Typ. Max.
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CXD5602GG SPI4 (VDD_CORE=1.0V(HP), VSS_DIG=0V reference, CL=15pF) Parameter Symbol Min. Typ. Max. Units Notes Chip Select Setup Time tLEAD tclk/2-2 ns Chip Select Hold Time tAG tclk-2 ns 25.7 ns Tx 103 ns Rx 10.256 ns Tx 41.2 ns Rx 10.256 ns Tx 41.2 ns Rx tCLK SCK Cycle tCLKWL SCK Pulse Width-High tCLKWL SCK Pulse Width-Low Data Output Delay Time tOD -3 8 ns Data Input Setup Time tsu 15 ns Data Input Hold Time tH 0 ns (VDD_CORE=0.
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CXD5602GG SPI5 (VDD_CORE=1.0V(HP), VSS_DIG=0V reference, CL=15pF) Parameter Symbol Min. Typ. Max. Chip Select Setup Time tLEAD tclk/2-5 ns Chip Select Hold Time tAG tclk-5 ns SCK Cycle tCLK 76.9 ns SCK Pulse Width-High tCLKWL 34.6 ns SCK Pulse Width-Low tCLKWL 34.6 ns Data Output Delay Time tOD -3 Data Input Setup Time tsu 12 ns Data Input Hold Time tH 0 ns 20 Units Notes ns (VDD_CORE=0.7V(LP), VSS_DIG=0V reference, CL=15pF) Parameter Symbol Min.
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CXD5602GG Slave Mode SPI2_CS_X (Input) t CLK t LEAD t AG SPI2_SCK (Input) t OD SPI2_MISO (Output) t SU tH SPI2_MOSI (Input) SPI2 (VDD_CORE=0.7V(LP)/1.0V(HP), VSS_DIG=0V reference, CL=30pF) Parameter Symbol Min. Typ. Max.
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CXD5602GG Quad SPI Flash Interface Quad SPI Flash Interface (SPI1) is available. tCHSH tSLCH SPI1_CS_X (Output) tSCK SPI1_SCK (Output) tSCKH tSCKL tOD SPI1_IO[3:0] (Output) tIS tIH SPI1_IO[3:0] (Input) (VDD_CORE=0.7V(LP)/1.0V(HP), VSS_DIG=0V reference, CL=15pF) Parameter Symbol Min. Typ. Max. Units Notes SPI1_SCK Period tSCK - 25.
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CXD5602GG Inter-integrated circuit interface (I2C) Up to four I2C bus interfaces can operate in multi-master mode (I2C0,I2C1,I2C2 and I2C4). They can support the standard (up to 100 kHz), and fast (up to 400 kHz) modes. And up to one I2C bus interface can operate slave mode (I2C3). They can support the standard (up to 100 kHz), fast (up to 400 kHz) and fast-mode plus (up to 1MHz).
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CXD5602GG Capacitive load for each bus line 73 CL 73 pF 4.7kohm PullUp I2C1 (VDD_CORE=0.7V(LP)/1.0V(HP), VSS_DIG=0V reference, CL= refer to table) Standard-Mode Parameter Fast-Mode - Symbol Min. Max. Min. Max. Min. Max. Units fSCL 0 100 0 400 - - kHz THD;STA 4.0 - 0.6 - - - us LOW period of the SCL clock tLOW 4.7 - 1.3 - - - us HIGH period of the SCL clock tHIGH 4.0 - 0.6 - - - us Setup time for a repeated START condition tSU;STA 4.7 - 0.
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CXD5602GG tFALL - 300 - 300 - - ns tSU;STO 4.0 - 0.6 - - - us Bus free time between STOP and START condition tBUF 4.7 - 1.3 - - - us - - Capacitive load for each bus line CL Fall time of both SDA and SCL signals Setup time for STOP condition 73 73 pF 4.7kohm PullUp I2C3 (Fast-Mode Plus is only supported for I2C3_BCK/I2C3_BDT) VDD_CORE=0.7V(LP)/1.0V(HP), VSS_DIG=0V reference, CL= refer to table) Standard-Mode Parameter Fast-Mode Fast-Mode Plus Symbol Min. Max. Min.
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CXD5602GG I2C4 (VDD_CORE=0.7V(LP)/1.0V(HP), VSS_DIG=0V reference, CL= refer to table) Standard-Mode Parameter Fast-Mode - Symbol Min. Max. Min. Max. Min. Max. Units fSCL 0 100 0 400 - - kHz THD;STA 4.0 - 0.6 - - - us LOW period of the SCL clock tLOW 4.7 - 1.3 - - - us HIGH period of the SCL clock tHIGH 4.0 - 0.6 - - - us Setup time for a repeated START condition tSU;STA 4.7 - 0.6 - - - us Data hold time; tHD;DAT - - - - - 5.
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CXD5602GG Universal Asynchronous Receiver Transmitter (UART) The device supports up to three universal asynchronous receiver transmitters (UART0, UART1 and UART2). UART0 and UART2 provide hardware management of the CTS and RTS signals (support flow control) .
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CXD5602GG Inter-integrated sound (I2S) Up to two I2S interfaces (I2S0 and I2S1) are available. LRCK tBLRS tBCKS tLRBS BCK tSDOBSS tSDOBHS tSDIBSS tSDIBHS SDOUT SDIN Serial Digital Interface Timing (Slave mode) LRCK tLRBM tBCKM BCK tSDOBSM tSDOBHM tSDIBSM tSDIBHM SDOUT SDIN Serial Digital Interface Timing (Master mode) Parameters Symbol Min Typ Max MCLK frequency FMCLK2 ‐ 24.
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CXD5602GG Unique Audio Data Format (Pulse Density Modulation) between CXD5602GG and CXD5247GF The audio master clock MCLK clock frequency is 24.567MHz (Typ.). The serialized audio signals PDM_CLK, PDM_IN and PDM_OUT are specified by MCLK.
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CXD5602GG Image Sensor Interface Parameter Input CLK Period Symbol dCK Min. Typ. Max. Units Notes - - - ns 54MHz Data input setup time tIS 4.5 - - ns - Data input hold time tiH 4.
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CXD5602GG SD Host Interface A SD host interface supports SD Memory Card Protocol version 3.0 in two different databus modes: 1-bit (default) and 4-bit. eMMC Interface An eMMC interface supports eMMC 4.41 Protocol compatible in two different databus modes: 1-bit (default) and 4-bit. Universal serial bus (USB) Device An USB Device is compliant with USB 2.0 Specification High-speed up to 480 Mbps.
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CXD5602GG RTC Signals RTC Signals are RTC_CLK_IN, PMIC_INT and RTC_IRQ_OUT. These signals are between CXD5602GG and CXD5247GF. Rise Edge Detection Mode tCLK RTC_CLK_IN (Input) tCLKWH tHOrise tSUrise PMIC_INT (Input) tODrise RTC_IRQ_OUT (Output) (VDDC=0.7V(LP)/1.0V(HP), Vss=0V reference, CL=25pF) Parameter Symbol Min. Typ. Max. Units tCLK - 30.51 - us RTC_CLK_IN Pulse Width-High tCLKWH 3.051 - 27.459 us Data Input Setup Time tSUrise 20.0 - - ns Data Input Hold Time tHOrise 2.
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CXD5602GG Fall Edge Detection Mode tCLK RTC_CLK_IN (Input) tCLKWH tHOfall tSUfall PMIC_INT (Input) tODfall RTC_IRQ_OUT (Output) (VDDC=0.7V(LP)/1.0V(HP), Vss=0V reference, CL=25pF) Parameter Symbol Min. Typ. Max. Units tCLK - 30.51 - us tCLKWH 3.051 - 27.459 us Data Input Setup Time tSUfall 20.0 - - ns Data Input Hold Time tHOfall 2.0 - - ns Data Output Delay Time tODfall 2.0 - 100.0 ns RTC_CLK_IN Clock Cycle RTC_CLK_IN Pulse Width-High 37 Notes RTC_CLK_IN = 32.
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CXD5602GG ADC Analog Input Interface HPADC analog input interface. (SEN_AIN0, SEN_AIN1) i Parameter Min. Typ. Max. Units Notes Conversion Rate 2 MS/s Input signal Bandwidth 32 kHz Input signal full scale 1.6 LPF -6dB 0.8 LPF 0.4 LPF through Vpp 0dB LPF +6dB 0.2 LPF +12dB 0.16 LPF +14dB Input signal range 1.44 Resolution Vpp LPF gain -6dB 0.72 LPF gain 0dB 0.36 LPF gain +6dB 0.18 LPF gain +12dB 0.144 LPF gain +14dB 10 bits DNL -1 2 LSB INL -4 4 LSB SNR 53.
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CXD5602GG Serial wire debug (SWD) The CXD5602GG provides the ARM SWD interface.
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CXD5602GG Notes on Handling The power supply and GND patterns have a large effect on undesired radiation on the board and interference to analog circuits, etc. Please refer to application notes of the CXD5602GG. Do not use this IC under conditions other than the recommended operating conditions. Absolute maximum rating values should not be exceeded even momentarily. It may damage the device, leading to eventual breakdown.
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CXD5602GG Pin Configuration I2C3, SPI2 and UART0 interfaces multiplexed with each other, so one interface is available.
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CXD5602GG Pin Description Pin Name Number (functions) C7 TEST0 Reset Type I/O IO Power Supply Digital I VDD_IO_DIG Hi-Z Alternate functions State D7 SYSTEM0 Digital I VDD_IO_DIG Hi-Z SWDCLK D8 SYSTEM1 Digital I/O VDD_IO_DIG Hi-Z SWDIO B8 BOOT_MODE Digital I VDD_IO_DIG PullDown C8 BOOT_REC Digital I VDD_IO_DIG PullDown E1 XOSC_IN Analog I/O - XOSC_IN - XOSC_OUT VDDA_SENS F1 XOSC_OUT Analog I/O A8 RTC_CLK_IN Digital I VDD_IO_DIG Hi-Z RTC_CLK_IN B9 R
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CXD5602GG Pin Name Number (functions) Type I/O IO Power Supply VDDA_SENS Reset Alternate functions State K1 SEN_AIN1 Analog I J2 SEN_AIN2 Analog I - H2 SEN_AIN3 Analog I - K2 SEN_AIN4 Analog I - L1 SEN_AIN5 Analog I - P5 P1e_00 Digital I/O VDD_IO_DIG Hi-Z SEN_IRQ_IN N5 P1f_00 Digital I/O VDD_IO_DIG Hi-Z SPI3_CS0_X M6 P1g_00 Digital I/O VDD_IO_DIG Hi-Z SPI3_CS1_X M5 P1h_00 Digital I/O VDD_IO_DIG Hi-Z SPI3_CS2_X N4 P1i_00 Digital I/O VDD_IO_DIG
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CXD5602GG Pin Name Number (functions) Reset Type I/O IO Power Supply P1o_03 Digital I/O VDD_IO_DIG Hi-Z P6 EMMC_CLK Digital I/O VDD_IO_DIG 0 N6 P1p_01 Digital I/O VDD_IO_DIG Hi-Z EMMC_CMD, SPI5_CS_XSPI5_SCK N7 P1p_02 Digital I/O VDD_IO_DIG Hi-Z EMMC_DATA0,SPI5_MOSI N8 P1p_03 Digital I/O VDD_IO_DIG Hi-Z EMMC_DATA1,SPI5_MISO M7 P1q_00 Digital I/O VDD_IO_DIG Hi-Z EMMC_DATA2 M8 P1q_01 Digital I/O VDD_IO_DIG Hi-Z EMMC_DATA3 P8 P1r_00 Digital I/O VDD_IO_DI
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CXD5602GG Pin Name Number (functions) C9 SWO Type I/O IO Power Supply Digital O VDD_IO_DIG 45 Reset State Hi-Z Alternate functions
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CXD5602GG Power Pins Pin Number Name Power Group J6,K6,K7, H6 VDD_CORE Vdd G9,H9,J9, F9 VDD_IO_DIG Vdd A3 VDDA_IO_ANA Vdd F2 VDDA_IO_SENS Vdd A2 VDDA_LNA Vdd C3 VDDA_LO Vdd B4 VDDA_ANA_M Vdd E3 VDDA_SYSPLL_M Vdd G1 VDDA_XOSC Vdd F3 VDDA_LPADC Vdd G3 VDDA_HPADC_M Vdd M3 VDDA_USB33 Vdd M2 VDDA_USB18_M Vdd L3 VDDA_USB10_M Vdd A7,A9,A10,A12,B14,D14,E5,E7,E8, VSS_DIG Vss E10,F6,F10,G6,G10,G11,G12, G13,G14,H5,H10,J5,J10,J11,J12,K5,K8 ,K9,P7P13,D9 A4, A5,B5,C5,D5,D4,
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CXD5602GG Ball Map MFC VFBGA 185pin.
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CXD5602GG Power On/Off sequence To avoid occurring reliability problem and loading external power supply system, turning on the I/O power supply(1.8V Domain) and then turning on the internal power supply(1.0/0.7V Domain) is recommended for power on. In addition, shutting down the internal power supply (1.0/0.7V Domain) and then shutting down the I/O power supply (1.8V Domain) in the reverse order of turning on is recommended for power off. VDDA_USB33 3.3V 3.0V VBUS OFF 3.3V Domain x80% 2.
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CXD5602GG CXD5602GG: MFC VFBGA 185pin 49
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CXD5602GG Application Circuits. Analog MIC. Fc is calculated using following formula. Fc=1/(2*pi*Ccoupling[0.01uF]*HPADC input impedance[1Mohm] External curcuits VDD CXD5602 0.1uF 0.01uF SEN_AIN HPADC Analog Input Signal HPF Fc=16Hz Input impedance is around 1M ohm.
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CXD5602GG Notice Purpose of Use of the Products: Customer shall use the Products with the utmost concern for safety, and shall not use the Products for any purpose that may endanger life or physical wellbeing, or cause serious damage to property or the environment, either through normal use or malfunction. Use of the Products for purposes other than those stipulated in this specification is strictly prohibited. Furthermore, usage of the Products for military purposes is strictly prohibited at all times.
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CXD5602GG NO ORAL OR WRITTEN INFORMATION OR ADVICE GIVEN BY SONY, ITS SUBSIDIARIES OR THEIR AUTHORIZED REPRESENTATIVES SHALL CREATE A WARRANTY, DUTY OR CONDITION OR IN ANY WAY INCREASE THE SCOPE OF THIS WARRANTY.