Datasheet

CXD5602GG
10
 Low power mode: 128fs, 64fs of bit clock frequency
 Sampling rate
 High performance mode
− Master mode : 192kHz, 96kHz, 48kHz
− Slave mode: 192kHz, 96kHz, 48kHz, 44.1kHz, 16kHz, 8kHz
 Low power mode
 Master mode : 96kHz, 48kHz
 Slave mode: 96kHz, 48kHz, 44.1kHz, 16kHz, 8kHz
 2ch channels each I2S interface
 Unique Audio Data Format (Pulse Density Modulation) between CXD5602GG and CXD5247GF
Clock, Reset and Power management Domain
The key features are:
 Reset
− Power on Reset from PMIC (CXD5247GF)
− Power on reset in RCOSC block
− Reset Caused by Watch Dog Timer
 RCOSC
− 8.192MHz
− Embedded Ring OSC
− Calibration by using RTC(32.768 kHz)
 XOSC
− XTAL: 26MHz
− Supply clock to RF-PLL and SysPLL
 Real Time Clock (RTC)
− Full clock features: sec, min, hour, date, day, month, and year
 PreCounter (15-bit)
 PostCounter (32-bit)
− 32.768 kHz operation
 Sys-PLL
− Lower power PLL on-chip System PLL which generates digital part.
 RF-PLL
− 196.416MHz
− PLL on-chip RF PLL which generates GNSS reference frequencies
 Watch Dog Timer (WDT)
− Reset requirement to external device at time out via I2C bus or GPIO
 Backup SRAM
− 64K-Byte SRAM
 ALIVE Connectivity to PMIC
− I2C bus interface