Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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AHB Master Bridge

The FFE AHB Master Bridge gives the Sensor Processing Subsystem FFE the ability to write directly to some of the EOS S3

platform resources. The following figure shows that this interface is composed of four functional units.

Figure 28: FFE AHB Master Bridge Block Diagram

AHB Protocol

Generator

Rate Matching

FIFO

AHB Master Bridge

AHB-to-AHB

Synchronous

Interface

FFE

Interface

Sensor Processing Subsystem

Flexible Fusion Engine

EOS System

The primary purpose for the AHB Master Bridge is to enable the Sensor Processing Subsystem FFE to conduct the

following operations:

• Enable the Sensor Processing Subsystems FFE to initiate updates of the FFE memories using the M4-F DMA

controller. This requires the M4-F to configure the DMA controller in advance of the FFE DMA request.

• Use sections of the M4-F memories as a large FIFO. This enables the storage of a larger amount of processed

sensor data than is available via other hardware paths.

Control Registers

The Control Registers block contains a series of register used for accessing the operations of the Sensor Processing

Subsystem. These registers include the following:

• Wishbone Bus access to multiple I

C and SPI Interfaces

• Access to the FFE and Sensor Manager (SM) memories

• Debug resources for both the FFE and SM

• Execution control and status for both the FFE and SM

• Interrupt resources for the Sensor Processing Subsystem

Packet FIFO

The Packet FIFO interface enables the FFE to pass sensor data in the form of packets to the EOS S3 platform. These

packets can contain either data resulting from Sensor Fusion processing or unprocessed sensor data. The format and

content of each packet is determined by the algorithm running on the FFE.

On-Chip Programmable Logic

The FFE has the capability to pass a Start signal to an IP in the on-chip programmable logic. Similarly, the IP in the on-

chip programmable logic can pass a Busy signal to the Sensor Processing Subsystem. The objective is to extend the

coordination of Sensor Fusion processing to IP in the on-chip programmable logic.