Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 83
8.6.1. Internal/External HSO Configuration
The configuration of internal or external High-Speed Oscillator (HSO) is configured by bootstrap pins IO_8 and IO_9.
When selecting the External HSO, the external clock is provided on IO_6.
Table 25: Internal/External HSO Configuration
IO_8 IO_9 Clock Source HSO
Configuration
Pulled Down (default) Pulled Down (default) Crystal or 32 kHz CMOS Clock at XTAL_IN Internal HSO
Pulled Down (default) Pulled Up Crystal or 32 kHz CMOS Clock at XTAL_IN Internal HSO
Pulled Up Pulled Down (default) 32 kHz CMOS Clock at XTAL_IN Internal HSO
Pulled Up Pulled Up IO_6 External HSO
8.6.2. SWD Debugger Present Configuration
The state of bootstrap pin IO_19 configures whether the SWD debugger is present.
NOTE: This setting only applies in AP configuration. In the Wearable configuration, bootstrap pin IO_19 must be pulled
down to allow operation of the SPI flash boot.
Table 26: SWD Debugger Present Configuration
IO_19 Debugger State
Pulled Down Debugger is not available until after the M4-F CPU core reset is
released.
Pulled Up Debugger access is allowed, as M4-F CPU core reset is released
immediately.
8.6.3. AP/Wearable Mode Configuration
The state of bootstrap pin IO_20 determines if the device is in AP mode (SPI Slave) or Wearable mode (SPI Master).
Table 27: AP/Wearable Mode Configuration
IO_20 Mode SPI Function SPI I/0s Used
Pulled Down Wearable Master IO_34 - SCLK IO_36 -
MISO IO_38 - MOSI
IO_39-SS1
Pulled Up AP Slave IO_16 - SCLK IO_17 -
MISO IO_19 - MOSI
IO_20 - CS
If in wearable mode, the M4-F CPU core reset is de-asserted automatically once the boot code is downloaded by
Configuration DMA.
If in AP mode, the application processor controls the release of the M4-F CPU core reset through register settings.