STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features • Core: ARM® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.
STM32F405xx, STM32F407xx • 8- to 14-bit parallel camera interface up to 54 Mbytes/s • True random number generator • CRC calculation unit Reference • 96-bit unique ID • RTC: subsecond accuracy, hardware calendar Table 1.
STM32F405xx, STM32F407xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.
Contents STM32F405xx, STM32F407xx 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 37 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 38 2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . .
STM32F405xx, STM32F407xx 6 7 Contents 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 112 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.16 I/O port characteristics . . . . . . . . .
List of tables STM32F405xx, STM32F407xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. 6/202 Device summary .
STM32F405xx, STM32F407xx Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92.
List of tables STM32F405xx, STM32F407xx Table 93. LQPF100 – 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 94. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 95. UFBGA176+25 ball, 10 × 10 × 0.
STM32F405xx, STM32F407xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39.
List of figures Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84.
STM32F405xx, STM32F407xx Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. List of figures recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 UFBGA176+25 ball, 10 x 10 mm, 0.
Introduction 1 STM32F405xx, STM32F407xx Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual which is available from the STMicroelectronics website www.st.com.
STM32F405xx, STM32F407xx 2 Description Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
Table 2.
Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix 3/2 (full duplex)(2) SPI / I2S I2C 3 USART/ UART 4/2 Communi USB cation OTG FS interfaces USB OTG HS Yes Yes CAN 2 SDIO Yes DocID022152 Rev 8 Camera interface GPIOs 12-bit ADC Number of channels No 51 72 Yes 82 114 72 82 114 140 13 16 24 24 LQFP144 UFBGA176 LQFP176 3 16 13 16 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 168 MHz 1.8 to 3.
Description 2.1 STM32F405xx, STM32F407xx Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family.
STM32F405xx, STM32F407xx Description Figure 2. Compatible board design STM32F10xx/STM32F2/STM32F40xxx for LQFP100 package 966 966 966 966 UHVLVWRU RU VROGHULQJ EULGJH SUHVHQW IRU WKH 670 ) [[[ FRQILJXUDWLRQ QRW SUHVHQW LQ WKH 670 ) [[ FRQILJXUDWLRQ 966 966 966 IRU 670 ) [[ 7ZR UHVLVWRUV FRQQHFWHG WR 9'' IRU 670 ) [[ 9'' 966 966 IRU WKH 670 ) [[ 966 IRU WKH 670 ) [[ 966 RU 1& IRU WKH 670 ) [[ DL G Figure 3.
Description STM32F405xx, STM32F407xx Figure 4. Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packages 6LJQDO IURP H[WHUQDO SRZHU VXSSO\ VXSHUYLVRU 3'5B21 9'' 966 7ZR UHVLVWRUV FRQQHFWHG WR 966 9'' RU 1& IRU WKH 670 ) [[ 9'' RU VLJQDO IURP H[WHUQDO SRZHU VXSSO\ VXSHUYLVRU IRU WKH 670 ) [[ 06 9 18/202 DocID022152 Rev 8
STM32F405xx, STM32F407xx 2.2 Description Device overview Figure 5. STM32F40xxx block diagram &&0 GDWD 5$0 .% 1-7567 -7', -7&. 6:&/. -7'2 6:' -7'2 -7$* 6: (70 $+% 038 19,& ([WHUQDO PHPRU\ FRQWUROOHU )60& 65$0 365$0 125 )ODVK 3& &DUG $7$ 1$1' )ODVK &/. 1( > @ $> @ '> @ 2(1 :(1 1%/> @ 1/ 15(* 1:$,7 ,25'< &' 1,25' ,2:5 ,17> @ 75$&(&/. ,171 1,,6 DV $) ' %86 , %86 ),)2 '0$ ),)2 ,' 9%86 62) '0$ 6WUHDPV ),)2 '0$ 6WUHDPV ),)2 51* 0% 65$0 .
Description 2.2.1 STM32F405xx, STM32F407xx ARM® Cortex®-M4 core with FPU and embedded Flash and SRAM The ARM Cortex-M4 processor with FPU is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
STM32F405xx, STM32F407xx 2.2.5 Description CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity.
Description STM32F405xx, STM32F407xx Figure 6. Multi-AHB matrix )#/$% $#/$% !##%, 53"?(3?- -!# 53" /4' %THERNET (3 %4(%2.%4?- $-!?0 '0 $-! $-!?-%- $-!?-%- '0 $-! $-!?0) 3 BUS ) BUS $ BUS !2#ORTEX - +BYTE ##- DATA 2!- &LASH MEMORY 32!- +BYTE 32!- +BYTE !(" PERIPHERALS !(" PERIPHERALS &3-# 3TATIC -EM#TL !0" !0" "US MATRIX 3 AI D 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each.
STM32F405xx, STM32F407xx 2.2.9 Description Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers.
Description STM32F405xx, STM32F407xx clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz.
STM32F405xx, STM32F407xx Description The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
Description STM32F405xx, STM32F407xx Figure 8. PDR_ON and NRST control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHW E\ RWKHU VRXUFH WKDQ SRZHU VXSSO\ VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 06 9 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. 2.2.
STM32F405xx, STM32F407xx Description Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions. All packages have regulator ON feature. Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Description STM32F405xx, STM32F407xx The following conditions must be respected: Note: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.8 V (see Figure 10).
STM32F405xx, STM32F407xx Description Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9 RU 9 9&$3B 9&$3B 9 0LQ 9 WLPH 1567 3$ DVVHUWHG H[WHUQDOO\ WLPH DL G 1. This figure is valid both whatever the internal reset mode (ON or OFF). 2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges. 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability Table 3.
Description STM32F405xx, STM32F407xx has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison.
STM32F405xx, STM32F407xx Description Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the V12 domain is controlled by an external power. 2.2.
Description STM32F405xx, STM32F407xx Table 4.
STM32F405xx, STM32F407xx Description General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40xxx devices (see Table 4 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F40xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler.
Description STM32F405xx, STM32F407xx SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 2.2.22 • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. Inter-integrated circuit interface (I²C) Up to three I²C bus interfaces can operate in multimaster and slave modes.
STM32F405xx, STM32F407xx Description Table 5. USART feature comparison Max. baud rate Max. baud rate Smartcard in Mbit/s in Mbit/s (ISO 7816) (oversampling (oversampling by 16) by 8) USART name Standard features Modem (RTS/ CTS) USART1 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) USART2 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) USART3 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) UART4 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) UART5 X - X - X - 2.62 5.25 APB1 (max.
Description 2.2.26 STM32F405xx, STM32F407xx Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
STM32F405xx, STM32F407xx Description The STM32F407xx includes the following features: 2.2.
Description 2.2.31 STM32F405xx, STM32F407xx Universal serial bus on-the-go high-speed (OTG_HS) The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s).
STM32F405xx, STM32F407xx Description alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 84 MHz. 2.2.
Description STM32F405xx, STM32F407xx Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 2.2.38 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
STM32F405xx, STM32F407xx Pinouts and pin description 6$$ 633 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! Figure 12. STM32F40xxx LQFP64 pinout 6"!4 0# 0# 0# 0( 0( .
Pinouts and pin description STM32F405xx, STM32F407xx 6$$ 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 13.
STM32F405xx, STM32F407xx Pinouts and pin description 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 14.
Pinouts and pin description STM32F405xx, STM32F407xx 3, 3, 3, 3, 9'' 3'5B21 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 9'' 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ 9'' 966 3, 3, Figure 15.
STM32F405xx, STM32F407xx Pinouts and pin description Figure 16. STM32F40xxx UFBGA176 ballout ! 0% 0% 0% 0% 0" 0" 0' 0' 0" 0" 0$ 0# 0! 0! 0! " 0% 0% 0% 0" 0" 0" 0' 0' 0' 0' 0$ 0$ 0# 0# 0! # 6"!4 0) 0) 0) 6$$ 0$2?/.
Pinouts and pin description STM32F405xx, STM32F407xx Figure 17. STM32F40xxx WLCSP90 ballout 0# 0$2?/. "//4 0" 0$ 0$ 0# 0! 6$$ 0# 6$$ 0" 0" 0$ 0$ 0! 0) 6#!0? 0! 633 0" 0" 0$ 0$ 0# 0) 0! 0! 0# "90!33? 2%' 0" 0" 0$ 0# 0! 0! 0! 0! % 0# 0# 633 633 6$$ 633 6$$ 0# 0# 0# & 0( 0( 0! 6$$ 0% 0% 6#!0? 0# 0$ 0$ ' .
STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
Pinouts and pin description STM32F405xx, STM32F407xx Table 8.
STM32F405xx, STM32F407xx Pinouts and pin description Table 8.
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10 /11 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2e xt SPI3/I2Sext /I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/2 TIM12/13/ 14 OTG_FS/ OTG_HS ETH FSMC/SDIO /OTG_FS DCMI PA0 - TIM2_CH1_ ETR TIM 5_CH1 TIM8_ETR - - - USART2_CTS UART4_TX - - ETH_MII_CRS - PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RTS UART4_RX - - ETH_MII _RX_CLK ETH_RMII__REF _CLK PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10 /11 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2e xt SPI3/I2Sext /I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/2 TIM12/13/ 14 OTG_FS/ OTG_HS ETH FSMC/SDIO /OTG_FS DCMI PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - - - - - OTG_HS_ULPI_ D1 ETH _MII_RXD2 - PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - - - - OTG_HS_ULPI_ D2 ETH _MII_RXD3 PB2 - - - - - - - - - - - PB3 JTDO/ TRACES WO
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10 /11 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2e xt SPI3/I2Sext /I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/2 TIM12/13/ 14 OTG_FS/ OTG_HS ETH FSMC/SDIO /OTG_FS DCMI PC0 - - - - - - - - - - OTG_HS_ULPI_ STP - - PC1 - - - - - - - - - - - ETH_MDC Port DocID022152 Rev 8 Port C AF14 AF15 - - EVENTOUT - - - EVENTOUT ETH _MII_TXD2 - - - EVENTOUT PC2 - - - - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10 /11 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2e xt SPI3/I2Sext /I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/2 TIM12/13/ 14 OTG_FS/ OTG_HS ETH FSMC/SDIO /OTG_FS DCMI PD0 - - - - - - - - - CAN1_RX - - FSMC_D2 - - EVENTOUT PD1 - - - - - - - - - CAN1_TX - - FSMC_D3 - - EVENTOUT PD2 - - TIM3_ETR - - - - - UART5_RX - - - SDIO_CMD DCMI_D11 - EVENTOUT PD3 -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10 /11 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2e xt SPI3/I2Sext /I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/2 TIM12/13/ 14 OTG_FS/ OTG_HS ETH FSMC/SDIO /OTG_FS DCMI Port Port E AF14 AF15 DocID022152 Rev 8 PE0 - - TIM4_ETR - - - - - - - - - FSMC_NBL0 DCMI_D2 - EVENTOUT PE1 - - - - - - - - - - - - FSMC_NBL1 DCMI_D3 - EVENTOUT PE2 TRACECL K - - - - - - - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10 /11 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2e xt SPI3/I2Sext /I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/2 TIM12/13/ 14 OTG_FS/ OTG_HS ETH FSMC/SDIO /OTG_FS DCMI PF0 - - - - I2C2_SDA - - - - - - - FSMC_A0 PF1 - - - - I2C2_SCL - - - - - - - FSMC_A1 - - - - - - - Port AF14 AF15 - - EVENTOUT - - EVENTOUT FSMC_A2 - - EVENTOUT PF2 - - - - I2C2_ SMBA P
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10 /11 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2e xt SPI3/I2Sext /I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/2 TIM12/13/ 14 OTG_FS/ OTG_HS ETH FSMC/SDIO /OTG_FS DCMI PG0 - - - - - - - - - - - - FSMC_A10 - - EVENTOUT PG1 - - - - - - - - - - - - FSMC_A11 - - EVENTOUT PG2 - - - - - - - - - - - - FSMC_A12 - - EVENTOUT PG3 - - - - - - - - - - - -
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10 /11 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2e xt SPI3/I2Sext /I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/2 TIM12/13/ 14 OTG_FS/ OTG_HS ETH FSMC/SDIO /OTG_FS DCMI PH0 - - - - - - - - - - - - - PH1 - - - - - - - - - - - - - PH2 - - - - - - - - - - - ETH _MII_CRS PH3 - - - - - - - - - - - Port AF14 AF15 - - EVENTOUT - - EVENTOUT - - - EVE
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10 /11 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2e xt SPI3/I2Sext /I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/2 TIM12/13/ 14 OTG_FS/ OTG_HS ETH FSMC/SDIO /OTG_FS DCMI PI0 - - TIM5_CH4 - - SPI2_NSS I2S2_WS - - - - - - - PI1 - - - - - SPI2_SCK I2S2_CK - - - - - - PI2 - - - TIM8_CH4 - SPI2_MISO I2S2ext_SD - - - - PI3 - - - TIM8_ETR - SPI2_MOSI I2S2_SD - - - -
STM32F405xx, STM32F407xx 4 Memory mapping Memory mapping The memory map is shown in Figure 18. Figure 18. STM32F40xxx memory map 2ESERVED #/24%8 - INTERNAL PERIPHERALS 2ESERVED !(" 2ESERVED X% X&&&& &&&& X% X% & &&&& X! X$&&& &&&& X! &&& X X # X &&& &&&& X "&& !(" X&&&& &&&& X% X$&&& &&&& -BYTE BLOCK #ORTEX - gS INTERNAL PERIPHERALS 2ESERVED X X X &&& &&&& X &&&& -BYTE BLOCK .
Memory mapping STM32F405xx, STM32F407xx Table 10.
STM32F405xx, STM32F407xx Memory mapping Table 10.
Memory mapping STM32F405xx, STM32F407xx Table 10.
STM32F405xx, STM32F407xx Memory mapping Table 10.
Electrical characteristics STM32F405xx, STM32F407xx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
STM32F405xx, STM32F407xx 5.1.6 Electrical characteristics Power supply scheme Figure 21. Power supply scheme 9%$7 9%$7 WR 9 *3,2V ,1 9&$3B 9&$3B î ) 9'' 966 î Q) î ) /HYHO VKLIWHU 287 9'' %DFNXS FLUFXLWU\ 26& . 57& :DNHXS ORJLF %DFNXS UHJLVWHUV EDFNXS 5$0 3RZHU VZLWFK ,2 /RJLF .HUQHO ORJLF &38 GLJLWDO 5$0 9ROWDJH UHJXODWRU )ODVK PHPRU\ %<3$66B5(* 3'5B21 9'' 9''$ 95() Q) ) 5HVHW FRQWUROOHU Q) ) 95(
Electrical characteristics 5.1.7 STM32F405xx, STM32F407xx Current consumption measurement Figure 22. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device.
STM32F405xx, STM32F407xx Electrical characteristics Table 12. Current characteristics Symbol Ratings Max.
Electrical characteristics STM32F405xx, STM32F407xx Table 14. General operating conditions (continued) Symbol Parameter Min Typ Max Unit 1.08 1.14 1.20 V VOS bit in PWR_CR register= 1 Max frequency 168MHz 1.20 1.26 1.32 V Regulator OFF: 1.2 V external voltage must be supplied from external regulator on VCAP_1/VCAP_2 pins Max frequency 144MHz 1.10 1.14 1.20 V Max frequency 168MHz 1.20 1.26 1.30 V Input voltage on RST and FT pins(6) 2 V ≤ VDD ≤ 3.6 V –0.3 - 5.5 VDD ≤ 2 V –0.
STM32F405xx, STM32F407xx Electrical characteristics Table 15. Limitations depending on the operating power supply range Operating power supply range ADC operation VDD =1.8 to 2.1 V(3) Conversion time up to 1.2 Msps VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps VDD = 2.4 to 2.7 V VDD = 2.7 to 3.6 V(5) Conversion time up to 2.4 Msps Conversion time up to 2.
Electrical characteristics 5.3.2 STM32F405xx, STM32F407xx VCAP_1/VCAP_2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP_1/VCAP_2 pins. CEXT is specified in Table 16. Figure 23. External capacitor CEXT & (65 5 /HDN 06 9 1. Legend: ESR is the equivalent series resistance. Table 16. VCAP_1/VCAP_2 operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.
STM32F405xx, STM32F407xx 5.3.5 Electrical characteristics Embedded reset and power control block characteristics The parameters given in Table 19 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 19. Embedded reset and power control block characteristics Symbol VPVD Parameter Conditions Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.04 2.
Electrical characteristics STM32F405xx, STM32F407xx Table 19. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit VBOR2 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 V Rising edge 2.53 2.59 2.63 V VBOR3 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 V Rising edge 2.85 2.92 2.97 V - - 100 - 0.5 1.5 3.
STM32F405xx, STM32F407xx Electrical characteristics Table 20.
Electrical characteristics STM32F405xx, STM32F407xx Table 21.
STM32F405xx, STM32F407xx Electrical characteristics Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF )$$ 25. M! # # # # # # #05 &REQUENCY -(Z -3 6 Figure 25.
Electrical characteristics STM32F405xx, STM32F407xx Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF )$$ 25. M! # # # # # # #05 &REQUENCY -(Z -3 6 Figure 27.
STM32F405xx, STM32F407xx Electrical characteristics Table 22.
Electrical characteristics STM32F405xx, STM32F407xx Table 23. Typical and maximum current consumptions in Stop mode Typ Symbol Parameter Supply current in Stop mode with main regulator in Run mode IDD_STOP Supply current in Stop mode with main regulator in Low-power mode Conditions Max TA = 25 °C TA = 25 °C Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.45 1.5 11.00 20.
STM32F405xx, STM32F407xx Electrical characteristics Table 25. Typical and maximum current consumptions in VBAT mode Max(1) Typ Symbol Parameter Backup IDD_VBA domain supply T current TA = 85 °C TA = 25 °C Conditions TA = 105 °C VBAT = 1.8 V VBAT= 2.4 V VBAT = 3.3 V VBAT = 3.6 V Backup SRAM ON, low-speed oscillator and RTC ON 1.29 1.42 1.68 6 11 Backup SRAM OFF, low-speed oscillator and RTC ON 0.62 0.73 0.96 3 5 Backup SRAM ON, RTC OFF 0.79 0.81 0.
Electrical characteristics STM32F405xx, STM32F407xx Figure 29.
STM32F405xx, STM32F407xx Electrical characteristics Additional current consumption The MCU is placed under the following conditions: • All I/O pins are configured in analog mode. • The Flash memory access time is adjusted to fHCLK frequency. • The voltage scaling is adjusted to fHCLK frequency as follows: – Scale 2 for fHCLK ≤ 144 MHz – Scale 1 for 144 MHz < fHCLK ≤ 168 MHz. • The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. • The HSE crystal clock frequency is 25 MHz.
Electrical characteristics STM32F405xx, STM32F407xx floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 28: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption.
STM32F405xx, STM32F407xx Electrical characteristics Table 27. Switching output I/O current consumption Symbol Parameter Conditions(1) I/O toggling frequency (fSW) Typ 2 MHz 0.02 8 MHz 0.14 25 MHz 0.51 50 MHz 0.86 60 MHz 1.30 2 MHz 0.10 8 MHz 0.38 25 MHz 1.18 50 MHz 2.47 60 MHz 2.86 2 MHz 0.17 8 MHz 0.66 25 MHz 1.70 50 MHz 2.65 60 MHz 3.48 2 MHz 0.23 8 MHz 0.95 25 MHz 3.20 50 MHz 4.69 60 MHz 8.06 2 MHz 0.30 8 MHz 1.22 25 MHz 3.90 50 MHz 8.
Electrical characteristics STM32F405xx, STM32F407xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 28. The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog pins by firmware. • All peripherals are disabled unless otherwise mentioned • The code is running from Flash memory and the Flash memory access time is equal to 5 wait states at 168 MHz.
STM32F405xx, STM32F407xx Electrical characteristics Table 28. Peripheral current consumption (continued) IDD(Typ)(1) Peripheral AHB2 (up to 168 MHz) AHB3 (up to 168 MHz) Scale2 (up t 168 MHz) (up to 144 MHz) OTG_FS 26.45 26.67 DCMI 5.87 5.35 RNG 1.50 1.67 FSMC 12.46 11.31 µA/MHz 13.10 11.81 µA/MHz TIM2 16.71 16.50 TIM3 12.33 11.94 TIM4 13.45 12.92 TIM5 17.14 16.58 TIM6 2.43 3.06 TIM7 2.43 2.22 TIM12 6.62 6.83 TIM13 5.05 5.47 TIM14 5.26 5.61 PWR 1.00 0.
Electrical characteristics STM32F405xx, STM32F407xx Table 28. Peripheral current consumption (continued) IDD(Typ)(1) Peripheral APB2 (up to 84 MHz) Scale1 Scale2 (up t 168 MHz) (up to 144 MHz) SDIO 7.08 7.92 TIM1 16.79 15.51 TIM8 17.88 16.53 TIM9 7.64 7.28 TIM10 4.89 4.82 TIM11 5.19 4.82 ADC1(5) 4.67 4.58 ADC2 (5) 4.67 4.58 ADC3 (5) 4.43 4.44 SPI1 1.32 1.39 USART1 3.51 3.72 USART6 3.55 3.75 SYSCFG 0.74 0.56 Unit µA/MHz 1.
STM32F405xx, STM32F407xx Electrical characteristics Table 29.
Electrical characteristics STM32F405xx, STM32F407xx Low-speed external user clock generated from an external source The characteristics given in Table 31 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 31.
STM32F405xx, STM32F407xx Electrical characteristics Figure 31. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU /6( WI /6( W W: /6( W: /6( 7/6( I/6(BH[W ([WHUQDO FORFN VRXUFH ,/ 26& B,1 670 ) DL High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator.
Electrical characteristics Note: STM32F405xx, STM32F407xx For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 32. Typical application with an 8 MHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I+6( 26&B,1 0+] UHVRQDWRU 5(;7 &/ 5) %LDV FRQWUROOHG JDLQ 26&B28 7 670 ) DL 1. REXT value depends on the crystal characteristics.
STM32F405xx, STM32F407xx Electrical characteristics Figure 33. Typical application with a 32.768 kHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I/6( 26& B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26& B28 7 &/ 670 ) DL 5.3.9 Internal clock source characteristics The parameters given in Table 34 and Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 34.
Electrical characteristics STM32F405xx, STM32F407xx Figure 34. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -3 6 5.3.10 PLL characteristics The parameters given in Table 36 and Table 37 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. Table 36.
STM32F405xx, STM32F407xx Electrical characteristics Table 36.
Electrical characteristics STM32F405xx, STM32F407xx Table 37. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz Min Typ Max Unit 0.15 0.45 - 0.40 0.75 mA - 0.40 0.85 mA 0.30 0.55 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2.
STM32F405xx, STM32F407xx Electrical characteristics With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz): INCSTEP = round [ ( ( 2 15 – 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] = 126md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized.
Electrical characteristics STM32F405xx, STM32F407xx Figure 36. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DL E 5.3.12 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 39. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.
STM32F405xx, STM32F407xx Electrical characteristics Table 40. Flash memory programming (continued) Symbol Parameter tERASE128KB Sector (128 KB) erase time tME Vprog Mass erase time Programming voltage Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism (PSIZE) = x 16 - 1.3 2.
Electrical characteristics STM32F405xx, STM32F407xx Table 41. Flash memory programming with VPP Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time Typ Max(1) Unit - 16 100(2) µs - 230 - - 490 - - 875 - - 6.9 - s TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V tERASE128KB Sector (128 KB) erase time tME Min(1) Mass erase time ms Vprog Programming voltage - 2.7 - 3.
STM32F405xx, STM32F407xx Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in Table 43. They are based on the EMS levels and classes defined in application note AN1709. Table 43. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.
Electrical characteristics STM32F405xx, STM32F407xx Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC? code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 44. EMI characteristics Symbol Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 25/168 MHz VDD = 3.
STM32F405xx, STM32F407xx Electrical characteristics Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 46. Electrical sensitivities Symbol LU 5.3.
Electrical characteristics STM32F405xx, STM32F407xx Table 47.
STM32F405xx, STM32F407xx Electrical characteristics Table 48. I/O static characteristics (continued) Symbol Parameter FT, TTa and NRST I/O input hysteresis VHYS BOOT0 I/O input hysteresis Ilkg RPU RPD CIO(8) Conditions Min Typ Max 1.7 V ≤VDD ≤3.6 V 10%VDD(3) - - 1.75 V ≤VDD ≤3.6 V -40 °C≤TA ≤105 °C V 0.
Electrical characteristics STM32F405xx, STM32F407xx Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
STM32F405xx, STM32F407xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 37 and Table 50, respectively. Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 50.
Electrical characteristics STM32F405xx, STM32F407xx Table 50. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Fmax(IO)out Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD > 2.70 V - - 100(4) CL = 30 pF, VDD > 1.8 V - - 50(4) CL = 10 pF, VDD > 2.70 V - - 180(4) CL = 10 pF, VDD > 1.8 V - - 100(4) CL = 30 pF, VDD > 2.
STM32F405xx, STM32F407xx 5.3.17 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 48). Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 51.
Electrical characteristics 5.3.18 STM32F405xx, STM32F407xx TIM timer characteristics The parameters given in Table 52 and Table 53 are guaranteed by design. Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 52.
STM32F405xx, STM32F407xx Electrical characteristics Table 53.
Electrical characteristics STM32F405xx, STM32F407xx SPI interface characteristics Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.
STM32F405xx, STM32F407xx Electrical characteristics Table 55. SPI dynamic characteristics(1) (continued) Symbol Parameter tw(SCKH) SCK high and low time tw(SCKL) Conditions Master mode, SPI presc = 2, 2.7V < VDD < 3.6V Master mode, SPI presc = 2, 1.7V < VDD < 3.
Electrical characteristics STM32F405xx, STM32F407xx Figure 39. SPI timing diagram - slave mode and CPHA = 0 166 LQSXW WF 6&. WVX 166 WK 166 WZ 6&.+ WU 6&. 6&. LQSXW &3+$ &32/ &3+$ &32/ WD 62 WZ 6&./ WY 62 WK 62 )LUVW ELW 287 0,62 RXWSXW WI 6&. 1H[W ELWV 287 WGLV 62 /DVW ELW 287 WK 6, WVX 6, )LUVW ELW ,1 026, LQSXW 1H[W ELWV ,1 /DVW ELW ,1 06Y 9 Figure 40. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW WF 6&. WVX 166 WZ 6&.+ WD 62 WZ 6&./ WI 6&. WK 166 6&.
STM32F405xx, STM32F407xx Electrical characteristics Figure 41. SPI timing diagram - master mode +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ WU 6&. WI 6&.
Electrical characteristics STM32F405xx, STM32F407xx I2S interface characteristics Unless otherwise specified, the parameters given in Table 56 for the i2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.
STM32F405xx, STM32F407xx Electrical characteristics Figure 42. I2S slave timing diagram (Philips protocol) &. ,QSXW WF &. &32/ &32/ WZ &.+ WK :6 WZ &./ :6 LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6% WUDQVPLW 06% WUDQVPLW WVX 6'B65 /6% UHFHLYH 6'UHFHLYH WK 6'B67 %LWQ WUDQVPLW /6% WUDQVPLW WK 6'B65 06% UHFHLYH %LWQ UHFHLYH /6% UHFHLYH DL E 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 43.
Electrical characteristics STM32F405xx, STM32F407xx USB OTG FS characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 57. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design. Table 58. USB OTG FS DC electrical characteristics Symbol Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit - 3.0(2) - 3.
STM32F405xx, STM32F407xx Electrical characteristics Figure 44. USB OTG FS timings: definition of data signal rise and fall time &URVV RYHU SRLQWV 'LIIHUHQWLDO GDWD OLQHV 9&56 966 WI WU DL E Table 59. USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter Rise time(2) tr tf Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.0 V Rise/ fall time matching trfm Output signal crossover voltage VCRS 1.
Electrical characteristics STM32F405xx, STM32F407xx Table 61. USB HS clock timing parameters(1) Parameter Symbol Frequency (steady state) ±500 ppm FSTEADY Duty cycle (first transition) DSTART_8BIT 8-bit ±10% Duty cycle (steady state) ±500 ppm DSTEADY Min Nominal Max Unit 59.97 60 60.03 MHz 40 50 60 % 49.975 50 50.025 % - - 1.
STM32F405xx, STM32F407xx Electrical characteristics Ethernet characteristics Unless otherwise specified, the parameters given in Table 64, Table 65 and Table 66 for SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 14 and VDD supply voltage conditions summarized in Table 63, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD.
Electrical characteristics STM32F405xx, STM32F407xx Figure 47. Ethernet RMII timing diagram 2-))?2%&?#,+ TD 48%. TD 48$ 2-))?48?%. 2-))?48$; = TSU 28$ TSU #23 TIH 28$ TIH #23 2-))?28$; = 2-))?#23?$6 AI Table 65. Dynamic characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 2 - - ns tih(RXD) Receive data hold time 1 - - ns tsu(CRS) Carrier sense set-up time 0.
STM32F405xx, STM32F407xx Electrical characteristics Table 66. Dynamic characteristics: Ethernet MAC signals for MII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 9 - tih(RXD) Receive data hold time 10 - tsu(DV) Data valid setup time 9 - tih(DV) Data valid hold time 8 - tsu(ER) Error setup time 6 - tih(ER) Error hold time 8 - td(TXEN) Transmit enable valid delay time 0 10 14 td(TXD) Transmit data valid delay time 0 10 15 Unit ns 1.
Electrical characteristics STM32F405xx, STM32F407xx Table 67. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - - 0.100 µs - - 3(7) 1/fADC - - 0.067 µs tlat(4) Injection trigger conversion latency fADC = 30 MHz tlatr(4) Regular trigger conversion latency fADC = 30 MHz tS(4) Sampling time tSTAB(4) Power-up time tCONV(4) Total conversion time (including sampling time) (7) - 2 fADC = 30 MHz 0.
STM32F405xx, STM32F407xx Electrical characteristics Equation 1: RAIN max formula R AIN ( k – 0.5 ) - – R ADC = --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. a Table 68.
Electrical characteristics STM32F405xx, STM32F407xx Figure 49. ADC accuracy characteristics ; ,3" )$%!, 6 2%& OR 6 $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AI C 1. See also Table 68. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5.
STM32F405xx, STM32F407xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 51 or Figure 52, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 51. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 ) 95() ) Q) 9''$ ) Q) 966$ 95() DL E 1.
Electrical characteristics STM32F405xx, STM32F407xx Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA) 670 ) 95() 9''$ ) Q) 95() 966$ DL F 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. 5.3.22 Temperature sensor characteristics Table 69.
STM32F405xx, STM32F407xx 5.3.23 Electrical characteristics VBAT monitoring characteristics Table 71. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 2 - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs Er (1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 5.3.
Electrical characteristics STM32F405xx, STM32F407xx Table 74. DAC characteristics (continued) Symbol RLOAD(2) Parameter Resistive load with buffer ON Min Typ Max Unit 5 - - kΩ Comments Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT Lower DAC_OUT voltage min(2) with buffer ON 0.
STM32F405xx, STM32F407xx Electrical characteristics Table 74. DAC characteristics (continued) Symbol Offset(4) Gain error(4) Parameter Min Typ Max Unit Comments - - ±10 mV Given for the DAC in 12-bit configuration Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error - - ±0.
Electrical characteristics STM32F405xx, STM32F407xx Figure 53. 12-bit buffered /non-buffered DAC %XIIHUHG 1RQ EXIIHUHG '$& %XIIHU 5/ '$&B287[ ELW GLJLWDO WR DQDORJ FRQYHUWHU &/ AI 6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.
STM32F405xx, STM32F407xx Electrical characteristics Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW .% &3-#?.% TV ./%?.% T W ./% T H .%?./% &3-#?./% &3-#?.7% TV !?.% &3-#?!; = T H !?./% !DDRESS TV ",?.% T H ",?./% &3-#?.",; = T H $ATA?.% T SU $ATA?./% TH $ATA?./% T SU $ATA?.% $ATA &3-#?$; = T V .!$6?.% TW .!$6 &3-#?.!$6 AI C 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 75.
Electrical characteristics STM32F405xx, STM32F407xx Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms WZ 1( )60&B1([ )60&B12( WY 1:(B1( W K 1(B1:( WZ 1:( )60&B1:( WK $B1:( WY $B1( )60&B$> @ $GGUHVV WY %/B1( )60&B1%/> @ WK %/B1:( 1%/ WY 'DWDB1( WK 'DWDB1:( 'DWD )60&B'> @ W Y 1$'9B1( )60&B1$'9 WZ 1$'9 DL 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 76.
STM32F405xx, STM32F407xx Electrical characteristics Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms TW .% &3-#?.% TV ./%?.% T H .%?./% &3-#?./% T W ./% &3-#?.7% TV !?.% &3-#?!; = T H !?./% !DDRESS TV ",?.% TH ",?./% &3-#?.",; = .", TH $ATA?.% TSU $ATA?.% T V !?.% &3-#? !$; = TSU $ATA?./% !DDRESS T V .!$6?.% TH $ATA?./% $ATA TH !$?.!$6 TW .!$6 &3-#?.!$6 AI B Table 77.
Electrical characteristics STM32F405xx, STM32F407xx Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms WZ 1( )60&B1([ )60&B12( WY 1:(B1( WZ 1:( W K 1(B1:( )60&B1:( WK $B1:( WY $B1( )60&B$> @ $GGUHVV WY %/B1( WK %/B1:( )60&B1%/> @ 1%/ W Y $B1( )60&B$'> @ W Y 'DWDB1$'9 $GGUHVV W Y 1$'9B1( WK 'DWDB1:( 'DWD WK $'B1$'9 WZ 1$'9 )60&B1$'9 DL % Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Min Max Unit FSMC_NE low time 4THCLK–0.
STM32F405xx, STM32F407xx Electrical characteristics 2. Guaranteed by characterization. Synchronous waveforms and timings Figure 58 through Figure 61 represent synchronous waveforms and Table 80 through Table 82 provide the corresponding timings.
Electrical characteristics STM32F405xx, STM32F407xx Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..
STM32F405xx, STM32F407xx Electrical characteristics Figure 59. Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &3-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+, .%X( &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, !$)6 TD #,+, $ATA TD #,+, $ATA TD #,+, !$6 !$; = &3-#?!$; = $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TD #,+, .",( &3-#?.
Electrical characteristics STM32F405xx, STM32F407xx Table 80. Synchronous multiplexed PSRAM write timings(1)(2) (continued) Symbol Parameter td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high tsu(NWAIT- FSMC_NWAIT valid before FSMC_CLK high CLKH) th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high Min Max Unit 0 - ns 4 - ns 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization. Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &3-#?#,+ TD #,+, .
STM32F405xx, STM32F407xx Electrical characteristics Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit 2THCLK –0.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0.
Electrical characteristics STM32F405xx, STM32F407xx Figure 61. Synchronous non-multiplexed PSRAM write timings TW #,+ "53452. TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, $ATA &3-#?$; = TD #,+, $ATA $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TD #,+, .",( TH #,+( .7!)46 &3-#?.", AI G Table 82.
STM32F405xx, STM32F407xx Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 62 through Figure 67 represent synchronous waveforms, and Table 83 and Table 84 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.
Electrical characteristics STM32F405xx, STM32F407xx Figure 63.
STM32F405xx, STM32F407xx Electrical characteristics Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read access )60&B1&( B WY 1&( B $ WK 1&( B $, )60&B1&( B +LJK )60&B$> @ )60&B1,2:5 )60&B1,25' WG 15(* 1&( B WK 1&( B 15(* )60&B15(* )60&B1:( WG 1&( B 12( WZ 12( WG 12( 1&( B )60&B12( WVX ' 12( WK 12( ' )60&B'> @ DL E 1. Only data bits 0...7 are read (bits 8...15 are disregarded).
Electrical characteristics STM32F405xx, STM32F407xx Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write access )60&B1&( B )60&B1&( B +LJK WY 1&( B $ WK 1&( B $, )60&B$> @ )60&B1,2:5 )60&B1,25' WG 15(* 1&( B WK 1&( B 15(* )60&B15(* WG 1&( B 1:( WZ 1:( )60&B1:( WG 1:( 1&( B )60&B12( WY 1:( ' )60&B'> @ DL E 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 66.
STM32F405xx, STM32F407xx Electrical characteristics Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access )60&B1&( B )60&B1&( B WY 1&([ $ WK 1&( B $, )60&B$> @ )60&B15(* )60&B1:( )60&B12( )60&B1,25' WG 1&( B 1,2:5 WZ 1,2:5 )60&B1,2:5 $77[+,= WK 1,2:5 ' WY 1,2:5 ' )60&B'> @ DL F Table 83.
Electrical characteristics STM32F405xx, STM32F407xx Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8THCLK –1 - ns - 5THCLK– 1 ns 8THCLK– 2 - ns - 5THCLK+ 2.5 ns 5THCLK–1.
STM32F405xx, STM32F407xx Electrical characteristics Figure 68. NAND controller waveforms for read access &3-#?.#%X !,% &3-#?! #,% &3-#?! &3-#?.7% TD !,% ./% TH ./% !,% &3-#?./% .2% TSU $ ./% TH ./% $ &3-#?$; = AI C Figure 69.
Electrical characteristics STM32F405xx, STM32F407xx Figure 70. NAND controller waveforms for common memory read access )60&B1&([ $/( )60&B$ &/( )60&B$ WG $/( 12( WK 12( $/( )60&B1:( WZ 12( )60&B12( WVX ' 12( WK 12( ' )60&B'> @ DL F Figure 71. NAND controller waveforms for common memory write access )60&B1&([ $/( )60&B$ &/( )60&B$ WG $/( 12( WZ 1:( WK 12( $/( )60&B1:( )60&B12( WG ' 1:( WY 1:( ' WK 1:( ' )60&B'> @ DL F Table 85.
STM32F405xx, STM32F407xx Electrical characteristics Table 86.
Electrical characteristics STM32F405xx, STM32F407xx Table 87. DCMI characteristics(1) (continued) Symbol Parameter Min Max 2.5 - tsu(DATA) Data input setup time th(DATA) Data hold time 1 - tsu(HSYNC), tsu(VSYNC) HSYNC/VSYNC input setup time 2 - th(HSYNC), th(VSYNC) HSYNC/VSYNC input hold time 0.5 - Unit ns 1. Guaranteed by characterization. 5.3.
STM32F405xx, STM32F407xx Electrical characteristics Figure 74. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Table 88. Dynamic characteristics: SD / MMC characteristics(1) Symbol fPP Parameter Conditions Min Typ Max Unit 48 MHz - Clock frequency in data transfer mode 0 SDIO_CK/fPCLK2 frequency ratio - - 8/3 tW(CKL) Clock low time fPP = 48 MHz 8.5 9 - tW(CKH) Clock high time fPP = 48 MHz 8.
Package information 6 STM32F405xx, STM32F407xx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 WLCSP90 package information Figure 75. WLCSP90 - 4.223 x 3.969 mm, 0.
STM32F405xx, STM32F407xx Package information Table 90. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.540 0.570 0.600 0.0213 0.0224 0.0236 A1 - 0.190 - - 0.0075 - A2 - 0.380 - - 0.0150 - (2) A3 - 0.025 - - 0.0010 - (3) 0.240 0.270 0.300 0.0094 0.0106 0.0118 D 4.188 4.223 4.258 0.1649 0.1663 0.1676 E 3.934 3.969 4.004 0.1549 0.1563 0.1576 e - 0.
Package information STM32F405xx, STM32F407xx Table 91. WLCSP90 recommended PCB design rules Dimension Recommended values Pitch 0.4 mm Dpad 260 µm max. (circular) 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed Device marking for WLCSP90 The following figure gives an example of topside marking and ball A1 position identifier location.
STM32F405xx, STM32F407xx LQFP64 package information Figure 78. LQFP64 – 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ 6($7,1* 3/$1( & $ $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( E ( 6.2 Package information H :B0(B9 1. Drawing is not to scale. Table 92. LQFP64 – 64-pin 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.
Package information STM32F405xx, STM32F407xx Table 92. LQFP64 – 64-pin 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 79.
STM32F405xx, STM32F407xx Package information Device marking for LQFP64 The following figure gives an example of topside marking and pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 80. LPQF64 marking example (package top view) 5HYLVLRQ FRGH 5 3URGXFW LGHQWLILFDWLRQ 670 ) 5*7 < :: 'DWH FRGH 3LQ LGHQWLILHU 06Y 9 1.
Package information 6.3 STM32F405xx, STM32F407xx LQPF100 package information Figure 81. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Table 93. LQPF100 – 100-pin, 14 x 14 mm low-profile quad flat package mechanical data(1) millimeters inches Symbol Min Typ Max Min Typ Max A - - 1.
STM32F405xx, STM32F407xx Package information Table 93. LQPF100 – 100-pin, 14 x 14 mm low-profile quad flat package mechanical data(1) (continued) millimeters inches Symbol Min Typ Max Min Typ Max E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1.
Package information STM32F405xx, STM32F407xx Device marking for LFP100 The following figure gives an example of topside marking and pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 83. LQFP100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) 5HYLVLRQ FRGH 9*7 5 'DWH FRGH < :: ^d ůŽŐŽ 3LQ LGHQWLILHU 06Y 9 1.
STM32F405xx, STM32F407xx LQFP144 package information Figure 84. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ & $ PP *$8*( 3/$1( ' / ' . $ FFF & / ' ( 3,1 ( ( E 6.4 Package information ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale.
Package information STM32F405xx, STM32F407xx Table 94. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.
STM32F405xx, STM32F407xx Package information Figure 85. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DL H 1. Dimensions are in millimeters.
Package information STM32F405xx, STM32F407xx Device marking for LQPF144 The following figure gives an example of topside marking and pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 86. LQFP144 marking example (package top view) 2SWLRQDO HMHFWRU KROH 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) =*7 'DWH FRGH <:: 3LQ LGHQWLILHU 2SWLRQDO HMHFWRU KROH 06Y 9 1.
STM32F405xx, STM32F407xx 6.5 Package information UFBGA176+25 package information Figure 87. UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline & ^ĞĂƚŝŶŐ ƉůĂŶĞ ϰ ĚĚĚ ϯ $ ϭ ď Ğ $ EDOO LGHQWLILHU ( $ EDOO LQGH[ DUHD $ ' Ğ Z ϭϱ ϭ KddKD s/ t E EDOOV dKW s/ t HHH 0 & $ III 0 & $ ( B0(B9 1. Drawing is not to scale. Table 95. UFBGA176+25 ball, 10 × 10 × 0.
Package information STM32F405xx, STM32F407xx Table 95. UFBGA176+25 ball, 10 × 10 × 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 88. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.
STM32F405xx, STM32F407xx Package information Device marking for UFBGA176+25 The following figure gives an example of topside marking and ball A 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 89. UFBGA176+25 marking example (package top view) 5HYLVLRQ FRGH 5 3URGXFW LGHQWLILFDWLRQ 670 ) ,*+ 'DWH FRGH %DOO $ LGHQWLILHU 06Y 9 1.
Package information 6.6 STM32F405xx, STM32F407xx LQFP176 package information Figure 90. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline C ! ! ! # 3EATING PLANE MM GAUGE PLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. Table 97. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.
STM32F405xx, STM32F407xx Package information Table 97. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max ZD - 1.250 - - 0.0492 - E 23.900 - 24.100 0.9409 - 0.9488 HE 25.900 - 26.100 1.0197 - 1.0276 ZE - 1.250 - - 0.0492 - e - 0.500 - - 0.0197 - 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - k 0° - 7° 0° - 7° ccc - - 0.080 - - 0.
Package information STM32F405xx, STM32F407xx Figure 91. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint 4?&0?6 1. Dimensions are expressed in millimeters.
STM32F405xx, STM32F407xx Package information Device marking for LQFP176 The following figure gives an example of topside marking and pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 92. LQFP176 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) ,*7 5HYLVLRQ FRGH < :: 'DWH FRGH 5 3LQ LGHQWLILHU 06Y 9 1.
Package information 6.7 STM32F405xx, STM32F407xx Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
STM32F405xx, STM32F407xx 7 Part numbering Part numbering Table 99.
Application block diagrams Appendix A A.1 STM32F405xx, STM32F407xx Application block diagrams USB OTG full speed (FS) interface solutions Figure 93. USB controller configured as peripheral-only and used in Full speed mode 6$$ 6 TO 6$$ 6OLATGE REGULATOR 6"53 $- /3#?). 0! 0" $0 0! 0" 633 /3#?/54 53" 3TD " CONNECTOR 34- & XX -3 6 1. External voltage regulator only needed when building a VBUS powered device. 2.
STM32F405xx, STM32F407xx Application block diagrams Figure 95. USB controller configured in dual mode and used in full speed mode 6$$ 6 TO 6$$ VOLTAGE REGULATOR 6$$ '0)/ )21 /VERCURRENT #URRENT LIMITER POWER SWITCH 6 0WR 34- & XX 0! 0" 0! 0" /3#?). /3#?/54 0! 0" 0! 0" 6"53 $$0 )$ 633 53"MICRO !" CONNECTOR '0)/ %. -3 6 1. External voltage regulator only needed when building a VBUS powered device. 2.
Application block diagrams A.2 STM32F405xx, STM32F407xx USB OTG high speed (HS) interface solutions Figure 96. USB controller configured as peripheral, host, or dual-mode and used in high speed mode 34- & XX &3 0(9 53" (3 /4' #TRL $0 $- NOT CONNECTED $0 5,0)?#,+ $- 5,0)?$; = 5,0) )$ 5,0)?$)2 6"53 5,0)?340 53" CONNECTOR 633 5,0)?.84 (IGH SPEED /4' 0(9 0,, 84 OR -(Z 84 -#/ OR -#/ 8) -3 6 1. It is possible to use MCO1 or MCO2 to save a crystal.
STM32F405xx, STM32F407xx A.3 Application block diagrams Ethernet interface solutions Figure 97. MII mode using a 25 MHz crystal 34- -#5 -))?48?#,+ -))?48?%. -))?48$; = -))?#23 -))?#/, %THERNET -!# (#,+ %THERNET 0(9 -)) PINS -))?28?#,+ -))?28$; = -))?28?$6 -))?28?%2 )%%% 040 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR -)) -$# PINS -$)/ -$# 003?/54 84!, -(Z /3# (#,+ 0,, 0(9?#,+ -(Z -#/ -#/ 84 -3 6 1. fHCLK must be greater than 25 MHz.
Application block diagrams STM32F405xx, STM32F407xx Figure 99. RMII with a 25 MHz crystal and PHY with PLL 34- & -#5 %THERNET 0(9 2-))?48?%. %THERNET -!# 2-))?48$; = 2-))?28$; = (#,+ )%%% 040 2-))?#28?$6 2-))?2%&?#,+ 2-)) PINS 2%&?#,+ -$)/ 4IMER INPUT TRIGGER 4IMESTAMP 4)- COMPARATOR 2-)) -$# PINS -$# OR OR -(Z SYNCHRONOUS -(Z 84!, -(Z /3# 0,, (#,+ 0,, -#/ -#/ 0(9?#,+ -(Z 84 -3 6 1. fHCLK must be greater than 25 MHz. 2.
STM32F405xx, STM32F407xx 8 Revision history Revision history Table 100. Document revision history Date Revision 15-Sep-2011 1 Initial release. 2 Added WLCSP90 package on cover page. Renamed USART4 and USART5 into UART4 and UART5, respectively. Updated number of USB OTG HS and FS in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts.
Revision history STM32F405xx, STM32F407xx Table 100. Document revision history (continued) Date 24-Jan-2012 192/202 Revision Changes Added V12 in Table 19: Embedded reset and power control block characteristics.
STM32F405xx, STM32F407xx Revision history Table 100. Document revision history (continued) Date 24-Jan-2012 Revision Changes Updated Table 61: USB HS clock timing parameters Updated Table 67: ADC characteristics. Updated Table 68: ADC accuracy at fADC = 30 MHz. Updated Note 1 in Table 74: DAC characteristics. Section 5.3.26: FSMC characteristics: updated Table 75 toTable 86, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms.
Revision history STM32F405xx, STM32F407xx Table 100. Document revision history (continued) Date 31-May-2012 194/202 Revision Changes 3 Updated Figure 5: STM32F40xxx block diagram and Figure 7: Power supply supervisor interconnection with internal reset OFF Added SDIO, added notes related to FSMC and SPI/I2S in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Starting from Silicon revision Z, USB OTG full-speed interface is now available for all STM32F405xx devices.
STM32F405xx, STM32F407xx Revision history Table 100. Document revision history (continued) Date 31-May-2012 Revision Changes Removed fHSE_ext typical value in Table 30: High-speed external user clock characteristics. Updated Table 32: HSE 4-26 MHz oscillator characteristics and Table 33: LSE oscillator characteristics (fLSE = 32.768 kHz). Added fPLL48_OUT maximum value in Table 36: Main PLL characteristics. Modified equation 1 and 2 in Section 5.3.
Revision history STM32F405xx, STM32F407xx Table 100. Document revision history (continued) Date 04-Jun-2013 196/202 Revision Changes 4 Modified Note 1 below Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Figure 4 title. Updated Note 3 below Figure 21: Power supply scheme. Changed simplex mode into half-duplex mode in Section 2.2.25: Interintegrated sound (I2S). Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and DAC_OUT2, respectively.
STM32F405xx, STM32F407xx Revision history Table 100. Document revision history (continued) Date 04-Jun-2013 Revision Changes Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline Updated Table 95: UFBGA176+25 ball, 10 × 10 × 0.
Revision history STM32F405xx, STM32F407xx Table 100. Document revision history (continued) Date 04-Jun-2013 198/202 Revision Changes Updated Figure 6: Multi-AHB matrix. Updated Figure 7: Power supply supervisor interconnection with internal reset OFF Changed 1.2 V to V12 in Section : Regulator OFF Updated LQFP176 pin 48. Updated Section 1: Introduction. Updated Section 2: Description. Updated operating voltage in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Note 1.
STM32F405xx, STM32F407xx Revision history Table 100. Document revision history (continued) Date 04-Jun-2013 Revision Changes Updated Table 64: Dynamic characteristics: Eternity MAC signals for SMI. Updated Table 66: Dynamic characteristics: Ethernet MAC signals for MII. Updated Table 79: Synchronous multiplexed NOR/PSRAM read timings. Updated Table 80: Synchronous multiplexed PSRAM write timings. Updated Table 81: Synchronous non-multiplexed NOR/PSRAM read 4 timings.
Revision history STM32F405xx, STM32F407xx Table 100. Document revision history (continued) Date 06-Mar-2015 200/202 Revision Changes 5 Replace Cortex-M4F by Cortex-M4 with FPU throughout the document. Updated Section : Regulator OFF and Table 3: Regulator ON/OFF and internal reset ON/OFF availability for LQFP176. Updated Figure 15: STM32F40xxx LQFP176 pinout and Table 7: STM32F40xxx pin and ball definitions. Updated Figure 6: Multi-AHB matrix.
STM32F405xx, STM32F407xx Revision history Table 100. Document revision history (continued) Date 22-Oct-2015 16-Mar-2016 09-Sep-2016 Revision Changes 6 In the whole document, updated notes related to values guaranteed by design or by characterization. Updated Table 34: HSI oscillator characteristics. Changed fVCO_OUT minimum value and VCO freq to 100 MHz in Table 36: Main PLL characteristics and Table 37: PLLI2S (audio PLL) characteristics.
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