Data Sheet

ManualsBrandsSparkfun Electronics ManualsAccelerometersSparkFun ±8g Triple Axis Accelerometer Breakout Board - MMA8452Q (Qwiic)

Freescale Semiconductor Document Number: MMA8452Q

Data Sheet: Technical Data Rev. 8.1, 10/2013

An Energy Efficient Solution by Freescale

Xtrinsic MMA8452Q 3-Axis,

12-bit/8-bit Digital Accelerometer

The MMA8452Q is a smart, low-power, three-axis, capacitive, micromachined

accelerometer with 12 bits of resolution. This accelerometer is packed with

embedded functions with flexible user programmable options, configurable to two

interrupt pins. Embedded interrupt functions allow for overall power savings

relieving the host processor from continuously polling data.

The MMA8452Q has user selectable full scales of ±2g/±4g/±8g with high-pass

filter filtered data as well as non-filtered data available real-time. The device can

be configured to generate inertial wakeup interrupt signals from any combination

of the configurable embedded functions allowing the MMA8452Q to monitor

events and remain in a low power mode during periods of inactivity. The

MMA8452Q is available in a 3 mm x 3 mm x 1 mm QFN package.

Features

• 1.95V to 3.6V supply voltage

• 1.6V to 3.6V interface voltage

• ±2g/±4g/±8g dynamically selectable full-scale

• Output Data Rates (ODR) from 1.56 Hz to 800 Hz

• 99 μg/√Hz noise

• 12-bit and 8-bit digital output

•I

digital output interface

• Two programmable interrupt pins for six interrupt sources

• Three embedded channels of motion detection

— Freefall or Motion Detection: 1 channel

— Pulse Detection: 1 channel

— Transient Detection: 1 channel

– Orientation (Portrait/Landscape) detection with set hysteresis

– Automatic ODR change for Auto-WAKE and return to SLEEP

– High-Pass Filter Data available real-time

–Self-Test

– RoHS compliant

– Current Consumption: 6 μA to 165 μA

Typical Applications

• E-Compass applications

• Static orientation detection (Portrait/Landscape, Up/Down, Left/Right, Back/

Front position identification)

• Notebook, e-reader, and Laptop Tumble and Freefall Detection

• Real-time orientation detection (virtual reality and gaming 3D user position feedback)

• Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup)

• Motion detection for portable product power saving (Auto-SLEEP and Auto-WAKE for cell phone, PDA, GPS, gaming)

• Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging)

•

User interface (menu scrolling by orientation change, pulse detection for button replacement

)

ORDERING INFORMATION

Part Number Temperature Range Package Description Shipping

MMA8452QT -40°C to +85°C QFN-16 Tray

MMA8452QR1 -40°C to +85°C QFN-16 Tape and Reel

MMA8452Q

16 PIN QFN

3 mm x 3 mm x 1 mm

CASE 2077-02

Top and Bottom View

Top View

Pin Connections

141516

876

VDD

VDDIO

BYP

SCL

GND

INT1

GND

INT2

SA0

SDA

Summary of content (47 pages)

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Freescale Semiconductor Data Sheet: Technical Data Document Number: MMA8452Q Rev. 8.1, 10/2013 An Energy Efficient Solution by Freescale Xtrinsic MMA8452Q 3-Axis, 12-bit/8-bit Digital Accelerometer MMA8452Q The MMA8452Q is a smart, low-power, three-axis, capacitive, micromachined accelerometer with 12 bits of resolution. This accelerometer is packed with embedded functions with flexible user programmable options, configurable to two interrupt pins.
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Contents 1 2 3 4 5 6 Block Diagram and Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Mechanical and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1 Block Diagram and Pin Description Internal OSC X-axis Transducer VDD VDDIO INT2 Embedded DSP Functions 12-bit ADC C to V Converter Y-axis Transducer VSS INT1 Clock GEN I2 C SDA SCL Z-axis Transducer Transient Detection (i.e.
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Figure 3 shows the device configuration in the six different orientation modes. These orientations are defined as the following: PU = Portrait Up, LR = Landscape Right, PD = Portrait Down, LL = Landscape Left, BACK and FRONT side views. There are several registers to configure the orientation detection and are described in detail in the register setting section.
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Table 1. Pin Descriptions Pin # Pin Name 1 VDDIO Description Power Supply for IO pins (1.62V - 3.6V) 2 BYP Bypass capacitor (0.1 μF) Input 3 NC Leave open. Do not connect.
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2 Mechanical and Electrical Specifications 2.1 Mechanical Characteristics Table 2. Mechanical Characteristics @ VDD = 2.5V, VDDIO = 1.8V, T = 25°C unless otherwise noted. Parameter Test Conditions Symbol Min FS[1:0] set to 00 2g Mode Measurement Range(1) Sensitivity FS[1:0] set to 01 4g Mode Typ FS ±4 ±8 FS[1:0] set to 00 2g Mode 1024 So g 512 FS[1:0] set to 10 8g Mode Sensitivity Accuracy(2) Unit ±2 FS[1:0] set to 10 8g Mode FS[1:0] set to 01 4g Mode Max counts/g 256 Soa ±2.
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2.2 Electrical Characteristics Table 3. Electrical Characteristics @ VDD = 2.5V, VDDIO = 1.8V, T = 25°C unless otherwise noted. Parameter Test Conditions Supply Voltage Interface Supply Voltage Symbol Min Typ Max Unit VDD(1) 1.95 2.5 3.6 V VDDIO(1) 1.62 1.8 3.6 V ODR = 1.56 Hz 6 ODR = 6.25 Hz 6 ODR = 12.5 Hz 6 ODR = 50 Hz Low-Power Mode ODR = 100 Hz 14 IddLP ODR = 200 Hz 44 ODR = 400 Hz 85 ODR = 800 Hz 165 ODR = 1.56 Hz 24 ODR = 6.25 Hz 24 ODR = 12.
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2.3 I2C interface characteristics Table 4. I2C slave timing values(1) Parameter Symbol I2C Fast Mode Min Max 400 Unit SCL clock frequency fSCL 0 Bus-free time between STOP and START condition tBUF 1.3 μs (Repeated) START hold time tHD;STA 0.6 μs Repeated START setup time tSU;STA 0.6 μs STOP condition setup time tSU;STO 0.6 kHz μs μs SDA data hold time tHD;DAT 0.05 SDA setup time tSU;DAT 100 ns SCL clock low time tLOW 1.3 μs SCL clock high time tHIGH 0.
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2.4 Absolute Maximum Ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5. Maximum Ratings Rating Symbol Value Unit Maximum Acceleration (all axes, 100 μs) gmax 5,000 g Supply Voltage VDD -0.3 to + 3.6 V Vin -0.3 to VDDIO + 0.3 V Drop Test Ddrop 1.
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4 Modes of Operation SLEEP ACTIVE OFF STANDBY WAKE Figure 6. MMA8452Q Mode Transition Diagram Table 7. Mode of Operation Description Mode OFF I2C Bus State Powered Down VDD VDDIO <1.8V VDDIO Can be > VDD Function Description The device is powered off. All analog and digital blocks are shutdown. I2C bus inhibited. STANDBY I2C communication with MMA8452Q is possible ON VDDIO = High VDD = High ACTIVE bit is cleared Only digital blocks are enabled. Analog subsystem is disabled.
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5 Functionality The MMA8452Q is a low-power, digital output 3-axis linear accelerometer with a I2C interface and embedded logic used to detect events and notify an external microprocessor over interrupt lines.
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5.1 Device Calibration The device interface is factory calibrated for sensitivity and Zero-g offset for each axis. The trim values are stored in Non Volatile Memory (NVM). On power-up, the trim parameters are read from NVM and applied to the circuitry. In normal use, further calibration in the end application is not necessary. However, the MMA8452Q allows the user to adjust the Zero-g offset for each axis after power-up, changing the default offset values.
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5.5.2 Motion Detection Motion is often used to simply alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. The motion detection function can analyze static acceleration changes or faster jolts.
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Top View PU Pin 1 Side View Earth Gravity BACK LL LR Xout @ 0g Yout @ -1g Zout @ 0g Xout @ 0g Yout @ 0g Zout @ -1g FRONT PD Xout @ -1g Yout @ 0g Zout @ 0g Xout @ 1g Yout @ 0g Zout @ 0g Xout @ 0g Yout @ 0g Zout @ 1g Xout @ 0g Yout @ 1g Zout @ 0g Figure 7. Landscape/Portrait Orientation Portrait 90° Portrait 90° Landscape to Portrait Trip Angle = 60° Portrait to Landscape Trip Angle = 30° 0° Landscape 0° Landscape (A) (B) Figure 8.
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5.9 Interrupt Register Configurations There are six configurable interrupts in the MMA8452Q: Data Ready, Motion/Freefall, Pulse, Orientation, Transient, and AutoSLEEP events. These six interrupt sources can be routed to one of two interrupt pins. The interrupt source must be enabled and configured. If the event flag is asserted because the event condition is detected, the corresponding interrupt pin, INT1 or INT2, will assert.
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5.10.1 I2C Operation The transaction on the bus is started through a start condition (START) signal. START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After START has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after START contains the slave address in the first 7 bits, and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave.
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Multiple Byte Write The MMA8452Q automatically increments the received register address commands after a write command is received. Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each MMA8452Q acknowledgment (ACK) is received. Table 10.
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6 Register Descriptions Table 11. Register Address Map Name Type Register Address Auto-Increment Address F_READ=0 Default Hex Value Comment 00000000 0x00 Real time status F_READ=1 STATUS(1)(2) R 0x00 OUT_X_MSB(1)(2) R 0x01 0x02 0x03 Output — [7:0] are 8 MSBs of 12-bit sample. OUT_X_LSB(1)(2) R 0x02 0x03 0x00 Output — [7:4] are 4 LSBs of 12-bit sample. OUT_Y_MSB(1)(2) R 0x03 0x04 0x05 Output — [7:0] are 8 MSBs of 12-bit sample.
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Table 11.
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ZYXOW is set whenever a new acceleration data is produced before completing the retrieval of the previous set. This event occurs when the content of at least one acceleration data register (i.e., OUT_X, OUT_Y, OUT_Z) has been overwritten. ZYXOW is cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the active channels are read. ZOW is set whenever a new acceleration sample related to the Z-axis is generated before the retrieval of the previous sample.
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Table 13. SYSMOD Description SYSMOD[1:0] System Mode. Default value: 00. 00: STANDBY mode 01: WAKE mode 10: SLEEP mode 0x0C: INT_SOURCE System Interrupt Status Register In the interrupt source register the status of the various embedded features can be determined. The bits that are set (logic ‘1’) indicate which function has asserted an interrupt and conversely the bits that are cleared (logic ‘0’) indicate which function has not asserted or has deasserted an interrupt.
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0x0D: WHO_AM_I Device ID Register The device identification register identifies the part. The default value is 0x2A. This value is factory programmed. Consult the factory for custom alternate values. 0x0D: WHO_AM_I Device ID Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 1 0 1 0 1 0 0x0E: XYZ_DATA_CFG Register The XYZ_DATA_CFG register sets the dynamic range and sets the high-pass filter for the output data. When the HPF_OUT bit is set.
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Table 18. High-Pass Filter Cutoff Options Oversampling Mode = Normal SEL1 SEL0 800 Hz 400 Hz 200 Hz 100 Hz 50 Hz 12.5 Hz 6.25 Hz 1.56 Hz 0 0 16 Hz 16 Hz 8 Hz 4 Hz 2 Hz 2 Hz 2 Hz 2 Hz 0 1 8 Hz 8 Hz 4 Hz 2 Hz 1 Hz 1 Hz 1 Hz 1 Hz 1 0 4 Hz 4 Hz 2 Hz 1 Hz 0.5 Hz 0.5 Hz 0.5 Hz 0.5 Hz 1 1 2 Hz 2 Hz 1 Hz 0.5 Hz 0.25 Hz 0.25 Hz 0.25 Hz 0.25 Hz Oversampling Mode = Low Noise Low Power 0 0 16 Hz 16 Hz 8 Hz 4 Hz 2 Hz 0.5 Hz 0.5 Hz 0.
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0x11: Portrait/Landscape Configuration Register This register enables the Portrait/Landscape function and sets the behavior of the debounce counter. 0x11: PL_CFG Register (Read/Write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBCNTM PL_EN 0 0 0 0 0 0 Table 20. PL_CFG Description DBCNTM PL_EN Debounce counter mode selection. Default value: 1 0: Decrements debounce whenever condition of interest is no longer valid. 1: Clears counter whenever condition of interest is no longer valid.
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0x14: P_L_THS_REG Portrait/Landscape Threshold and Hysteresis Register This register represents the Portrait to Landscape trip threshold. 0x14: P_L_THS_REG Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P_L_THS[4] P_L_THS[3] P_L_THS[2] P_L_THS[1] P_L_THS[0] HYS[2] HYS[1] HYS[0] : Table 24. P_L_THS_REG Description P_L_THS[7:3] HYS[2:0] Portrait/Landscape Fixed Threshold angle = 1_0000 (45°).
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0x15: FF_MT_CFG Freefall/Motion Configuration Register This is the Freefall/Motion configuration register for setting up the conditions of the freefall or motion function. 0x15: FF_MT_CFG Register (Read/Write) Bit 7 ELE Bit 6 OAE Bit 5 ZEFE Bit 4 YEFE Bit 3 XEFE Bit 2 0 Bit 1 0 Bit 0 0 Table 26. FF_MT_CFG Description ELE OAE ZEFE YEFE XEFE Event Latch Enable: Event flags are latched into FF_MT_SRC register. Reading of the FF_MT_SRC register clears the event flag EA and all FF_MT_SRC bits.
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Table 27. Freefall/Motion Source Description EA ZHE ZHP YHE YHP XHE XHP Event Active Flag. Default value: 0. 0: No event flag has been asserted; 1: one or more event flag has been asserted. See the description of the OAE bit to determine the effect of the 3-axis event flags on the EA bit. Z Motion Flag. Default value: 0. 0: No Z Motion event detected, 1: Z Motion has been detected This bit reads always zero if the ZEFE control bit is set to zero Z Motion Polarity Flag. Default value: 0.
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0x18: FF_MT_COUNT Debounce Register This register sets the number of debounce sample counts for the event trigger. 0x18: FF_MT_COUNT_Register (Read/Write) Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 Table 29. FF_MT_COUNT Description Count value. Default value: 0000_0000 D[7:0] This register sets the minimum number of debounce sample counts of continuously matching the detection condition user selected for the freefall, motion event.
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High-g Event on all 3-axis (Motion Detect) Count Threshold (a) FF Counter Value FFEA High-g Event on all 3-axis (Motion Detect) DBCNTM = 1 Count Threshold Debounce Counter Value (b) EA High-g Event on all 3-axis (Motion Detect) DBCNTM = 0 Count Threshold Debounce Counter Value (c) EA Figure 13. DBCNTM Bit Function MMA8452Q Sensors Freescale Semiconductor, Inc.
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6.4 Transient (HPF) Acceleration Detection For more information on the uses of the transient function please review Freescale application note, AN4071. This function is similar to the motion detection except that high-pass filtered data is compared. There is an option to disable the high-pass filter through the function. In this case the behavior is the same as the motion detection. This allows for the device to have 2 motion detection functions.
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0x1F: TRANSIENT_THS Register The Transient Threshold register sets the threshold limit for the detection of the transient acceleration. The value in the TRANSIENT_THS register corresponds to a g value which is compared against the values of High-Pass Filtered Data. If the HighPass Filtered acceleration value exceeds the threshold limit, an event flag is raised and the interrupt is generated if enabled.
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6.5 Single, Double and Directional Pulse-Detection Registers For more details of how to configure the pulse detection and sample code, please refer to Freescale application note, AN4072. The pulse-detection registers are referred to as “Pulse”. 0x21: PULSE_CFG Pulse Configuration Register This register configures the event flag for the pulse detection for enabling/disabling the detection of a single and double pulse on each of the axes.
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0x23 - 0x25: PULSE_THSX, Y, Z Pulse Threshold for X, Y & Z Registers The pulse threshold can be set separately for the X, Y and Z axes. The PULSE_THSX, PULSE_THSY and PULSE_THSZ registers define the threshold which is used by the system to start the pulse detection procedure. 0x23: PULSE_THSX Register (Read/Write) Bit 7 0 Bit 6 THSX6 Bit 5 THSX5 Bit 4 THSX4 Bit 3 THSX3 Bit 2 THSX2 Bit 1 THSX1 Bit 0 THSX0 Bit 2 THSY2 Bit 1 THSY1 Bit 0 THSY0 Table 38.
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Table 43. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 0 ODR (Hz) Max Time Range (s) Time Step (ms) Normal LPLN HighRes LP Normal LPLN HighRes LP 800 0.159 0.159 0.159 0.159 0.625 0.625 0.625 0.625 400 0.159 0.159 0.159 0.319 0.625 0.625 0.625 1.25 200 0.319 0.319 0.159 0.638 1.25 1.25 0.625 2.5 100 0.638 0.638 0.159 1.28 2.5 2.5 0.625 5 50 1.28 1.28 0.159 2.55 5 5 0.625 10 12.5 1.28 5.1 0.159 10.2 5 20 0.625 40 6.25 1.28 5.1 0.
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0x28: PULSE_WIND Register (Read/Write) 0x28: PULSE_WIND Second Pulse Time Window Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WIND7 WIND6 WIND5 WIND4 WIND3 WIND2 WIND1 WIND0 Table 47. PULSE_WIND Description WIND[7:0] Second Pulse Time Window. Default value: 0000_0000.
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6.6 Auto-WAKE/SLEEP Detection The ASLP_COUNT register sets the minimum time period of inactivity required to change current ODR value from the value specified in the DR[2:0] register to ASLP_RATE register value, provided the SLPE bit is set to a logic ‘1’ in the CTRL_REG2 register. See Table 52 for functional blocks that may be monitored for inactivity in order to trigger the “return to SLEEP” event.
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6.7 Control Registers Note: Except for STANDBY mode selection, the device must be in STANDBY mode to change any of the fields within CTRL_REG1 (0X2A). 0x2A: CTRL_REG1 System Control 1 Register 0x2A: CTRL_REG1 Register (Read/Write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ASLP_RATE1 ASLP_RATE0 DR2 DR1 DR0 LNOISE F_READ ACTIVE Table 53. CTRL_REG1 Description ASLP_RATE[1:0] DR[2:0] LNOISE F_READ ACTIVE Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode.
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0x2B: CTRL_REG2 System Control 2 Register 0x2B: CTRL_REG2 Register (Read/Write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ST RST 0 SMODS1 SMODS0 SLPE MODS1 MODS0 Table 57. CTRL_REG2 Description ST RST SMODS[1:0] SLPE MODS[1:0] Self-Test Enable. Default value: 0. 0: Self-Test disabled; 1: Self-Test enabled Software Reset. Default value: 0. 0: Device reset disabled; 1: Device reset enabled. SLEEP mode power scheme selection. Default value: 00.
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0x2C: CTRL_REG3 Interrupt Control Register 0x2C: CTRL_REG3 Register (Read/Write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 WAKE_TRANS WAKE_LNDPRT WAKE_PULSE WAKE_FF_MT 0 IPOL PP_OD Table 60. CTRL_REG3 Description WAKE_TRANS WAKE_LNDPRT WAKE_PULSE WAKE_FF_MT IPOL PP_OD 0: Transient function is bypassed in SLEEP mode. Default value: 0. 1: Transient function interrupt can wake up system 0: Orientation function is bypassed in SLEEP mode. Default value: 0.
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0x2E: CTRL_REG5 Register (Read/Write) 0x2E: CTRL_REG5 Interrupt Configuration Register Bit 7 Bit 6 INT_CFG_ASLP 0 Bit 5 Bit 4 Bit 3 Bit 2 INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE INT_CFG_FF_MT Bit 1 Bit 0 0 INT_CFG_DRDY Table 62. Interrupt Configuration Register Description Interrupt Configuration Description INT1/INT2 Configuration. Default value: 0. 0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin INT1/INT2 Configuration. Default value: 0.
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Table 66.
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Table 66. MMA8452Q Register Map 2E CTRL_REG5 Control Reg5 (Interrupt Configuration) R/W INT_CFG_ASLP 0 INT_CFG_TRANS INT_CFG_LNDPR T INT_CFG_PULSE INT_CFG_FF_MT 0 INT_CFG_DRD Y 2F OFF_X X 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0 30 OFF_Y Y 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0 31 OFF_Z Z 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0 Table 67. Accelerometer Output Data 12-bit Data Range ±2g (1 mg) Range ±4g (2 mg) Range ±8g (3.9 mg) 0111 1111 1111 1.999g +3.
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PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN MMA8452Q Sensors Freescale Semiconductor, Inc.
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PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN MMA8452Q 44 Sensors Freescale Semiconductor, Inc.
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PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN MMA8452Q Sensors Freescale Semiconductor, Inc.
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Table 68. Revision history Revision number Revision date Description of changes 5 07/2012 • Table 2. Updated Typ values for Sensitivity Accuracy from 2.5% to 2.68%; Zero-g Level Offset Accuracy from ±20 mg to ±17 mg and Zero-g Level Offset Accuracy Post Board Mount from ±30 mg to ±20 mg. • Updated section 2.3 I2C Interface Characteristics • Added Table 8. Features of the MMA845xQ devices. • Removed FIFO paragraph at the end of Section 6.1. • Updated Case outline. 6 02/2013 • Replaced Section 2.
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