Data Sheet

ICM-20948
Document Number: DS-000189 Page 29 of 89
Revision: 1.3
Data Format / Acknowledge
I
2
C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data
transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge
signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and
holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can
hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and
releases the clock line (refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
DATA OUTPUT BY
RECEIVER (SDA)
SCL FROM
MASTER
START
condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
1 2 8 9
Figure 9. Acknowledge on the I
2
C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an
8
th
bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the
slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device.
Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line
LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the master with
a STOP condition (P), thus freeing the communications line. However, the master can generate a repeated START
condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to HIGH transition on
the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the
exception of start and stop conditions.
SDA
START
condition
SCL
ADDRESS R/W
ACK DATA ACK DATA ACK
STOP
condition
S P
1 – 7 8 9 1 – 7 8 9 1 – 7 8 9
Figure 10. Complete I
2
C Data Transfer