Data Sheet

October 2017 BNO080 Datasheet 1000-3927
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Parameter
Symbol
Min
Typ
Max
Unit
SPI (CLK) clock frequency
3
MHz
SPI clock period
tck
0.33
µs
SCL high period
tckh
0.5*tck
SCL low period
tckl
0.5*tck
CS setup to CLK
tcssu
0.1
µs
CS hold
tcssh
16.83
Ns
CS to MISO out
tcsso
31
ns
CLK to MISO out valid
tsov
35
ns
MISO hold
tsoh
13.7
ns
MISO hold after CS
tcssoh
7.4
ns
MOSI setup time
tsisu
25
ns
MOSI hold time
tsih
5.4
ns
Figure 6-6: SPI timing parameters
Figure 6-7: SPI timing
6.5.3 Interrupt timing
In SPI and I
2
C mode the HOST_INTN signal is used by the BNO080 to indicate to the application processor that
the BNO080 needs attention. The signal is active low and is asserted until either the end of the I
2
C device
address is registered or the SPI chip select is observed.
Figure 6-8: Host interrupt timing – I
2
C mode
If the BNO080 is asleep the host can wake it by assertion of the wake signal. The BNO080 will assert the interrupt
line to indicate it is awake. If the BNO080 interrupted the host then it is already awake.
tcssu
tsoh
D7 D6 D5 D4 D2 D1 D0D3
D7 D6 D5 D4 D2 D1 D0D3
CS
CLK
MISO
MOSI
tsisu
tsov
tcssh
tcsso
tsih
twckh
twckl
tck
tcssoh
Start
D7D6D5D4D3D2D1D0 ACK
tclid
H_INTN
H_SCL
H_SDA