User's Manual
Table Of Contents
- 1. General Description
- 2. Installation and Operation
- 3. Options
- 3.1 T01 Programmable Channel Spacing
- 3.2 T02 Programmable CTCSS encoder/decoder
- 3.3 T03 Programmable DCS/CTCSS encoder/decoder
- 3.4 T05 Balanced and Isolated VF plus E&M
- 3.5 T06 Simplex Changeover Relay
- 3.6 T08 VF Delay
- 3.7 T09 300Hz Upgrade HPF Filter
- 3.8 T10 Power Save Mode
- 3.9 T11 Combined Options
- 3.10 T12 External Reference Oscillator Input
- 3.11 T13 Local Speaker, Mic Socket and Front Panel Mute
- 3.12 T14 Local Channel Change
- 3.13 T16 1PPM Frequency Stability
- 3.14 U69 Extended Temperature Range Verification
- 3.15 T19/26 Line Interface Board.
- 3.16 T29 Balanced and Isolated VF plus E&M
- 3.17 T31 Network Adapter
- 3.18 T34 Ethernet option
- 3.19 T36 Option - TX Ref Oscillator input and Modulator
- 6. MX800 Base Station Fault Finding Procedure
- 7. Appendices
- 7.1 MX800 Interface Connections
- 7.2 CN2 DB9 Female Monitor Connector
- 7.3 CN3 DB25 Female Digital I/O Connector
- 7.4 MX800 Specifications
- 7.5 Channel Select DIP Switch Settings
- 7.6 MX800 Model Number Configuration Guide
- 7.7 MX800 System Applications
- 7.7.1 Conventional base station/repeater
- 7.7.2 Link transceiver
- 7.7.3 Data transceiver
- 7.7.4 Paging transmitter
- 7.7.5 Trunking Base Station
- 7.7.6 Systems base
- 7.7.7 Repeater with Morse ID
- 7.7.8 Simplex base station
- 7.7.9 Duplicated base station
- 7.7.10 Power Save base station
- 7.7.11 Tone key base station
- 7.7.12 Voting base station
- 7.7.13 Simulcast base station
- 8. Superseded Technical Information
- 9. Drawings
Technical Manual Appendices
7.3 CN3 DB25 Female Digital I/O Connector
Each CMOS logic input is protected by a 10K Ohm series resistor to the input
of the logic chip. There is also a 10K Ohm pull up/down resistor at each input
so as to default the input value to that set by JMP19. Each logic output is
protected by a 1K-Ohm series resistor from the output of the logic chip.
Pin No Function
13 DIGITAL EARTH or +5VDC output. JMP15 selectable.
25 INPUT PORT A. 8-bit Logic Input bit 0. (Power control bit 0)or Digital
CTCSS Control bit 0
12 INPUT PORT A. 8-bit Logic Input bit 1. (Power control bit 1)or Digital
CTCSS Control bit 1
24 INPUT PORT A. 8-bit Logic Input bit 2. (RX CTCSS control)or Digital
CTCSS Control bit 2
11 INPUT PORT A. 8-bit Logic Input bit 3. (TX CTCSS control)or Digital
CTCSS Control bit 3
23 INPUT PORT A. 8-bit Logic Input bit 4. (N/W address bit 0)
10 INPUT PORT A. 8-bit Logic Input bit 5. (N/W address bit 1)
22 INPUT PORT A. 8-bit Logic Input bit 6. (N/W address bit 2)
9 INPUT PORT A. 8-bit Logic Input bit 7. (N/W address bit 3)
21 INPUT PORT B. Channel Select BCD Units bit 0. / Binary Bit 0.
8 INPUT PORT B. Channel Select BCD Units bit 1. / Binary Bit 1.
20 INPUT PORT B. Channel Select BCD Units bit 2. / Binary Bit 2.
7 INPUT PORT B. Channel Select BCD Units bit 3. / Binary Bit 3.
19 INPUT PORT B. Channel Select BCD Tens bit 0. / Binary Bit 4.
6 INPUT PORT B. Channel Select BCD Tens bit 1. / Binary Bit 5.
18 INPUT PORT B. Channel Select BCD Tens bit 2. / Binary Bit 6.
5 INPUT PORT B. Channel Select BCD Tens bit 3. / Binary Bit 7.
17 OUTPUT PORT C. 8-bit Logic Output bit 7.
4 OUTPUT PORT C. 8-bit Logic Output bit 6.
16 OUTPUT PORT C. 8-bit Logic Output bit 5.
3 OUTPUT PORT C. 8-bit Logic Output bit 4.
15 OUTPUT PORT C. 8-bit Logic Output bit 3.(Digital CTCSS Control bit 3)
2 OUTPUT PORT C. 8-bit Logic Output bit 2. (Digital CTCSS Control bit 2)
14 OUTPUT PORT C. 8-bit Logic Output bit 1. (Digital CTCSS Control bit 1)
1 OUTPUT PORT C. 8-bit Logic Output bit 0. (Digital CTCSS Control bit 0)
Table 7-4 CN3 Connections
© SPECTRA ENGINEERING 2008 Revision 4.3.1B
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