Technical Manual

ATLAS 4500 Multimode Station Technical Manual December 2016 A-3
380-520 MHz Exciter Module Appendix A - UHF Circuit Descriptions
Synthesizer IC24 and associated components provide a reference of 120.45 MHz
for the error loop second mixer LO amp IC21. This 120.45 MHz signal is frequency
locked to the 10 MHz main reference clock.
Synthesizer IC22 and associated components provide a reference of 40.32 MHz for
the MCLK line to the A/D IC 31. This 40.32 MHz signal is frequency locked to the
43.2 MHz FPGA ADLMX line.
A.1.2.2 TX VCO Board
The plug on VCO board consists of 4 band high Q inductor oscillators with a
common base oscillator for low phase noise. This is contained in a shielded
compartment in the case. The VCO provides frequencies over 499.64 – 639.64
MHz range in 4 bands.
The main RF VCO OUT on SKJ-6 is first buffered by a very high isolation circuit
consisting of the MMIC on the VCO, then on main board, a 3 dB pad and an
amplifier IC17. It is then down-converted at mixer X8 and used to generate the
main transmit RF amplifier signal source.
Each band is switched under control of the Controller. 2 MMIC buffers feed the
synthesizer and main outputs. The power supply to the VCO consists of an 8-V
regulator and active filter for maximum noise rejection located on the exciter PCB.
The 8-V supply consists of IC11, TR6 and associated components.
The PLL control line varies VCO frequency (SKT – 1).
A.1.2.3 Reference Clocks
A stable 10 MHz reference is generated by X1—a temperature controlled crystal
oscillator, and is fed to the synthesizer IC6 through select switch IC7. A detector
circuit senses the presence of an external 10 MHz reference > approximately 0 dBm
(0.6 Vpp) and informs the Controller through EXT REF DET CN3 – 10. IC7
switches between this internal oscillator and an external 10 MHz reference source
fed into CN4 under control of the Controller through EXT OSC SW CN3-13.
Buffer transistors TR2 and TR3 provide a fast slew rate clock REF IN for better
phase noise. This feeds a digital buffer IC 29 generating a fast edge 10MHz clock
for the 345.6 MHz and 120.47 MHz synthesizers.
There is a time delay to re-initialize the exciter after changing from internal to
external clock or external to internal clock, due to synthesizers needing re-
programming by the controller.
NOTE
An external 10 MHz clock must have low phase noise/jitter and have a nominal level of 10 dBm
(1.8 Vpp)