Technical Manual

ATLAS 4500 Multimode Station Technical Manual December 2016 A-5
380-520 MHz Exciter Module Appendix A - UHF Circuit Descriptions
The feedback signal from the Power Amplifier sample port comes into the exciter
module through CN6 at approximately 3 dBm. This is attenuated then down-
converted with the main VCO output (499.64
—639.64 MHz) from buffer amp
IC16 by mixer M1 to provide an output of 119.64 MHz. This passes through a 150
MHz low pass filter and is amplified by IC15.
The 119.64 MHz IF is down-converted with the 120.45 MHz local signal from
buffer amp IC21 by mixer M2 to result in an 810 KHz IF signal.
The local oscillator for this second down converter is provided by the 120.45 MHz
Synthesizer IC24 and associated components. Programming for this is provided by
the FPGA IC32.
The 810 KHz IF signal is band pass filtered and then amplified by a 20 dB gain
differential amplifier IC14, then further amplified by the 16 dB gain differential
amplifier front end of IC31, a high performance Analog-to-Digital converter.
This IF signal is sampled at a 20.16 MSps rate, then passed through an 810 kHz
digital FIR band pass filter inside IC31, BW is approximately 100 kHz and
decimated by 8 for a 2.5 MSps O/P rate.
The 16 bit digital samples from IC31 are read by IC32, the main FPGA/ARM for
processing by internal software. An area for pre-distortion correction tables is
provided by IC27 RAM. The FPGA DPD filter data is stored in the serial Flash
ROM IC35.
Inside the FPGA IC the 2.52 MSps 810 kHz IF is decimated by 7 to effectively give
a 1/9 converted 360 MSps 90 kHz signal plus other unwanted signals. This is then
passed though a narrow 90 kHz IF band pass FIR filter to removing other products
and noise.
The correction software in the FPGA/ARM has a short initial delay acquisition
followed by I/Q correction. This allows corrections to reduce overall distortion
products at the PA output.
A.1.2.7 Exciter DC Supplies
The exciter is supplied a nominal 13.8 V through CN3-2. This input supply is then
distributed to IC1, IC4, IC9 and IC11.
IC1 is configured as a 1 MHz buck DC-DC converter and provides the main
regulated +5.2 VDC output. A shielded inductor is used to reduce fields.
NOTE
The sample port CN2 provides a -6 dB sample of one side of the final differential analog O/P of
the 810 kHz IF at approximately a -10 dBm level.