Technical Manual

A-4 ATLAS 4500 Multimode Station Technical Manual July 2016
767-870 MHz Exciter Module Appendix A - 700/800 MHz Circuit Descriptions
Buffer transistors TR2 and TR3 provide a fast slew rate clock REF IN for better
phase noise. This feeds a digital buffer IC 29 generating a fast edge 10MHz clock
for the 345.6 MHz and 120.47 MHz synthesizers.
There is a time delay to re-initialize the exciter after changing from internal to
external clock or external to internal clock, due to synthesizers needing re-
programming by the controller.
A.1.2.4 RF Carrier Generation & Modulation
RF carrier modulation type Phase 1 FM or LSM and Phase 2 H-DQPSK is
generated within IC31 FPGA and IC32 DDS from a serial digital stream on the I2S
bus lines coming from the external digital signal processor (DSP) and fed into Pins
5, 7 and 8 of CN3. The initial setup for the FPGA internal Arm controller is done
through the I2C bus on Pins 9 and 12 of CN3. The ARM controller inside the
FPGA IC has a 20 MHz crystal clock and internal VCO.
The FPGA provides raised cosine filtering of the I/Q data and is sent in digital form
to the DDS digital I/Q modulator. The DDS IC generates a differential 119.64 MHz
I/Q modulated signal. This is filtered by the SAW filter F5 into the high level mixer
X8 input.
The VCO output signal is mixed with the 119.64 MHz modulated signal by mixer
X8 (O/P of ~ -23 dBm) at the desired transmitter output frequency.
A.1.2.5 RF Filter Amp Section
The RF output of the mixer X8 is fed through the first RF band pass filter, then the
first MMIC amp, then the second RF band pass filter, and finally the second MMIC
amp before being output to the Power Amplifier module through CN1.
The 760 – 870 MHz band pass filter function is supplied by selectable bands. 2
bands are fitted as standard 760- 775 MHz and 850 – 870 MHz.
Each first band pass filter I/P is fed by switch IC20, then the filter output into IC18,
then first amp IC2, to make up a selector circuit that switches the frequency band
programmed by the Controller. This is followed by first MMIC amp IC2 and next a
fixed attenuator.
Each second filter I/P is fed by Switch IC26, then the filter output into IC19, for the
frequency band of operation. The second RF MMIC amp IC23 provides gain for
this stage to the O/P at a ~ 13 dBm output level.
NOTE
An external 10 MHz clock must have low phase noise/jitter and have a nominal level of 10 dBm
(1.8 Vpp)