User's Manual

NRM7292D NRM7292D Specification (US) User Manual P a g e | 6
___________________________________________________________________________________
© Copyright SRF 2020. All rights reserved.
Table 3.1 NRM7292D signal description
Pad No Name Direction Volt Description
1 GROUND GND
2 GROUND GND
3 GROUND GND
4 GROUND GND
5 VDD_FEM P Front End Module power input
6 VBAT P NRC7292 power input
7 GROUND GND
8 GROUND GND
9 MODE_00 I
SW Define (When ROM BOOT)
11: Internal SRAM BOOT
10 MODE_01 I
11 MODE_02 I
0: ROM BOOT
1: XIP BOOT
12 MODE_03 I
0: Cortex-M0 Master
1: Cortex-M3 Master
13 MODE_04 I
0: Two CPU
1: One CPU
14 GROUND GND
15 HSPI_nCS I Host SPI – Chip Select (active low)
16 HSPI_CLK I Host SPI – Clock
17 HSPI_MISO O Host SPI – Master in Slave out
18 HSPI_MOSI I Host SPI – Master out Slave in
19 HSPI_EIRQ O Host SPI – Interrupt
20 GROUND GND
21 GROUND GND
22 NC -
23 NC -
24 NC -
25 GP_00_UART2_TX I/O UART Channel2 Tx
26 GP_01_UART2_RX I/O UART Channel2 Rx
27 GP_02_UART2_RTS I/O UART Channel2 RTS
28 GP_03_UART2_CTS I/O UART Channel2 CTS
29 GP_04_UART0_TX I/O UART Channel0 Tx
30 GP_05_UART0_RX I/O UART Channel0 Rx
31 GP_06_UART3_TX I/O UART Channel3 Tx
32 GP_07_UART3_RX I/O UART Channel3 Rx
33 GP_08_UART1_RX I/O UART Channel1 Rx