User's Manual

LD2103 V2.8 Page 31 of 36
SRT Marine
Instruction Manual
SRT-MTB
©
Class B Marine AIS
Block Schematics – Baseband Block Diagram
5502A
200MHz
1.26V core
SDRAM
2Mx32
FLASH
4Mb
ProASIC3
FPGA
1.5V core
12.288MHz
Triple Rail Monitor
12V, 3.3V & 1.26V
TPS3307-18
AIC23A
STEREO
CODEC 48K
McBSP
1V5
rms
Opto input
RS422 output
Asynchronous
Receiver/Transmitter
UART 1
GPIO (with readback)
DSP
EMIF
Interface
UART baud rate
generator
To RF section
12V to RF PA
Protection &
suppresion
2 x 8 0.1" header, user I/O
SYNTH SPI
Controller
RESET
FPGA
Watchdog
JTAG
JTAG
header
INTn
CODEC SET-UP
CONTROLLER
DAC
CONTROL
ADC
DATA
Internal
GPS
receiver
RS232
level converter
(optional)
Asynchronous
Receiver/Transmitter
UART 2
Asynchronous
Receiver/Transmitter
UART 4
6V Switch mode
power supply
5V Linear
power supply
3V3 Linear
power supply
1V25 LDO
2V5 / 1V5 LDO
SERIAL DATA
8 CH ADC
TLV0838
7 X 1 .1"
DEBUG hdr
Spare_10-14
EEPROM
SPI
interface
EEPROM
25LC320
(optional)
External
User
interface
3V3 serial
3V3 serial
3V3 serial
3.3V
TTL
Synth
SPI BUS
TXE 1 TXE 2 TXE 3
LNA ON
LDSYNTH 1 LDSYNTH 2
RF SYSTEM CLK
SERIAL DATA
5 X 1 .1"
DEBUG hdr
EMIF BUS
Tx lockout timer
and logic
Watchdog timer
and logic
Psuedo Random
Pattern Generator
UART 0
JTAGJTAG hdr