User's Manual

February 2017
DocID0xxxxx Rev 0.xx 16/27
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change
without notice. ww w.st.com
3.3 Layout guidelines
When adopting SPSGPE, please consider the following guidelines for a correct PCB design:
1. A minimum four-layer PCB is suggested.
2. At least one of the PCB layers should be used to implement a copper ground plane
without cuts.
3. Copper planes and/or heavy traces are recommended to implement power supply
connections.
4. Decoupling capacitors (recommended values are 100 nF and 10 µF in parallel) have to
be placed very close to power supply pins.
5. Routing of traces (especially noisy and high frequency ones) across the power supply
should be avoided.
6. The ANT pin (pin TP45) needs to be used for connecting the module to an external
antenna. Its related RF ground is represented by pins TP44 and TP46. A trace having a
controlled impedance of 50 Ω needs to be used to connect the ANT pin (pin TP45) to an
external antenna (microstrip or grounded coplanar waveguide solutions of 50 Ω are
suggested).
7. Routing of traces (especially noisy, high frequency and power supply ones) near or
across the connection between the ANT pin (pin TP45) and the external antenna should
be avoided.
8. Connection of all ground metallization and/or layers should have as many vias as
possible. Number and density of these vias should be increased in the connection area
between the ANT pin (pin TP45) and the external antenna.
9. A differential trace of 90 Ω needs to be used to connect pins TP18 and TP19 (USB_P /
RTS and USB_N / CTS, respectively) to a USB connector, in case they are used as USB
traces. It is also strongly recommended to follow all hardware and layout guidelines by
USB standards.
An example of SPSGPE layout is pictured in
Figure 4.