AN5866 Application note Guidelines for cycling endurance and data retention performances on page EEPROM Introduction This application note details the ST page EEPROM cycling and data retention performances. Reliability and endurance are key requirements for datalogging or event recording applications. A very high level of quality is consequently mandatory for these electronic applications. This application note applies to the Page EEPROMs products listed in Table 1. Table 1.
AN5866 Page EEPROM cycling performance 1 Page EEPROM cycling performance 1.1 Cycling budget Page EEPROMs can write data with: • • Page Program operation that needs erased bytes (FFh) to program data Page Write operation that is a Page Erased followed by a Page Program operation For more information about Page Program and Page Write operations refer to the application note AN5747 (Page EEPROM memory architecture). Table 2.
AN5866 Cycling qualification method 1.2 Cycling qualification method The qualification cycling pattern is defined to reach three weeks (~ 500 h cycling time) as defined in JEDEC JESD47. During the qualification phase, the page EEPROM parts are cycled and then read to locate eventual failing bit. Page EEPROM architecture embeds DMU (data memory unit) as illustrated in the figure below: Figure 1.
AN5866 Page EEPROMs cycling strategies 2 Page EEPROMs cycling strategies Simple recommendations and good cycling strategy can really optimize the cycling endurance of page EEPROM products. As a power-down during a page write cycle can corrupt the whole addressed page, the areas containing the read-only parameters and the cycled items should be separated and made as much as possible independent from each other. These two types of data should not share the same pages.
AN5866 Page EEPROM strategy 2: data class budget 2.2 Page EEPROM strategy 2: data class budget The second cycling strategy recommends the designer to allocate enough memory for a data class. The memory allocated is calculated with the total amount of cycles the data class realizes during the whole application lifetime. If different data class are cycled, several parts of the memory should be allocated for each data class type.
AN5866 Page EEPROM data retention 3 Page EEPROM data retention 3.1 Definition At t0, bytes are written, after what no page write or erase operations are executed on these bytes. The data retention time is the time after t0 during which the bytes can still be correctly read (the page EEPROM devices being DC supplied or not). 3.2 Data retention and temperature dependence Page EEPROMs data retention is temperature dependent. The higher is the temperature the lower is the data retention time.
AN5866 Data retention qualification method Figure 5. Page EEPROM data retention time vs temperature (cycled page) At average 40°C, if the page is cycled, the data programmed in a page EEPROM product can be read for 10 years. 3.3 Data retention qualification method Data retention qualification procedure for page EEPROM checks that the data remain readable with a safe programming level.
AN5866 Application data retention strategy Table 3. Example of data retention capability calculation Temperature (°C) Application temperature (years)(1) Data retention capability (years) Data retention usage (%)(2) 30 14 232 6 50 6 56 10.7 TOTAL: 16.7% 1. The maximum data retention is determined with the Figure 4 2. The data retention capability is calculated with the [1] The data is safe for 20 years, with only 16.7% of data retention capability used.
AN5866 Conclusion 4 Conclusion The budget of 500 k cycles per page is defined by the number of page write and erase operations executed over the page. Page program operations and ECC are irrelevant regarding the cycling budget of page EEPROM products. Moreover, this cycling budget is not depending on the temperature and voltage ranges, which makes page EEPROM very handy.
AN5866 Revision history Table 4. Document revision history AN5866 - Rev 1 Date Version 16-Feb-2023 1 Changes Initial release.
AN5866 Contents Contents 1 2 3 4 Page EEPROM cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Cycling budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Cycling qualification method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Overall number of cycles . . . . . . . . . .
AN5866 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Applicable products . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of data retention capability calculation . Document revision history . . . . . . . . . . . . . . . . AN5866 - Rev 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN5866 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. AN5866 - Rev 1 M95P32 DMU architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page EEPROM pages counting cycling strategy . . . . . . . . . . . . . . . Cycling Strategy with data class budget . . . . . . . . . . . . . . . . . . . . . Page EEPROM data retention time vs temperature (Read-only data). Page EEPROM data retention time vs temperature (cycled page) . . . . . . . . . . . . . . . . . .
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