L6205 DMOS DUAL FULL BRIDGE DRIVER ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 5.6A OUTPUT PEAK CURRENT (2.8A DC) RDS(ON) 0.3Ω TYP.
L6205 ABSOLUTE MAXIMUM RATINGS Symbol VS VOD VBOOT Parameter Test conditions Value Unit Supply Voltage VSA = VSB = VS 60 V Differential Voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS = 60V; VSENSEA = VSENSEB = GND 60 V Bootstrap Peak Voltage VSA = VSB = VS VS + 10 V VIN,VEN Input and Enable Voltage Range -0.
L6205 THERMAL DATA Symbol Description Rth-j-pins MaximumThermal Resistance Junction-Pins Rth-j-case Maximum Thermal Resistance Junction-Case PowerDIP20 SO20 PowerSO20 Unit 12 14 - °C/W - - 1 °C/W 40 51 - °C/W Rth-j-amb1 MaximumThermal Resistance Junction-Ambient Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient 2 - - 35 °C/W Rth-j-amb1 MaximumThermal Resistance Junction-Ambient 3 - - 15 °C/W Rth-j-amb2 Maximum Thermal Resistance Junction-Ambient 4 56 77 62 °C/W
L6205 PIN DESCRIPTION PACKAGE SO20/ PowerDIP20 PowerSO20 PIN # PIN # 1 Name Type Function 6 IN1A Logic Input Bridge A Logic Input 1. 2 7 IN2A Logic Input Bridge A Logic Input 2. 3 8 SENSEA Power Supply Bridge A Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. 4 9 OUT1A Power Output Bridge A Output 1. 5, 6, 15, 16 1, 10, 11, 20 GND GND 7 12 OUT1B Power Output Bridge B Output 1.
L6205 ELECTRICAL CHARACTERISTICS (Tamb = 25 °C, Vs = 48V, unless otherwise specified) Symbol Min Typ Max Unit VSth(ON) Turn-on Threshold 6.6 7 7.4 V VSth(OFF) Turn-off Threshold 5.6 6 6.4 V 5 10 mA IS Tj(OFF) Parameter Quiescent Supply Current Test Conditions All Bridges OFF; Tj = -25°C to 125°C (7) Thermal Shutdown Temperature °C 165 Output DMOS Transistors RDS(ON) High-Side Switch ON Resistance Tj = 25 °C Low-Side Switch ON Resistance IDSS Leakage Current 0.34 0.
L6205 ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25 °C, Vs = 48V, unless otherwise specified) Symbol tD(off)IN tFALL Parameter Test Conditions Input to out turn OFF delay time ILOAD =2.8A, Resistive Load Output Fall Time (8) ILOAD =2.8A, Resistive Load tdt Dead Time Protection fCP Charge pump frequency Min Typ Max 600 ns 40 0.5 -25°C
L6205 Figure 2.
L6205 CIRCUIT DESCRIPTION POWER STAGES and CHARGE PUMP The L6205 integrates two independent Power MOS Full Bridges. Each Power MOS has an Rdson=0.3ohm (typical value @ 25°C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a dead time (td = 1µs typical) between the switch off and switch on of two Power MOS in one leg of a bridge. Using N Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage.
L6205 NON-DISSIPATIVE OVERCURRENT PROTECTION The L6205 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short circuit to ground or between two phases of the bridge. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 7 shows a simplified schematic of the overcurrent detection circuit.
L6205 Figure 8.
L6205 Figure 9. tDISABLE versus CEN and REN (VDD = 5V). R EN = 2 20 kΩ 3 1 .1 0 R EN = 1 00 kΩ R EN = 4 7 kΩ R EN = 3 3 kΩ tDISABLE [µs] R EN = 1 0 kΩ 100 10 1 1 10 1 00 C E N [n F ] Figure 10. tDELAY versus CEN (VDD = 5V). tdelay [µs] 10 1 0.1 1 10 Cen [nF] 100 THERMAL PROTECTION In addition to the Ovecurrent Protection, the L6205 integrates a Thermal Protection for preventing the device destruction in case of junction over temperature.
L6205 APPLICATION INFORMATION A typical application using L6205 is shown in Fig. 11. Typical component values for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6205 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching.
L6205 PARALLELED OPERATION The outputs of the L6205 can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges.
L6205 Figure 13. Parallel connection with lower Overcurrent Threshold + VS 8-52VDC VSA C1 17 VSB C2 POWER GROUND - D1 CBOOT SIGNAL GROUND RP D2 14 VCP 19 11 ENA ENB 12 SENSEA 1 3 SENSEB 2 8 OUT1A 4 OUT2A 18 OUT1B 7 OUT2B REN EN CEN CP VBOOT LOAD 20 9 10 16 15 6 13 5 IN1A IN2A INA IN1B INB IN2B GND GND GND GND D02IN1360 It is also possible to parallel the four Half Bridges to obtain a simple Half Bridge as shown in Fig.
L6205 OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION In Fig. 15 and Fig. 16 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving two loads, for two different driving types: – One Full Bridge ON at a time (Fig. 15) in which only one load at a time is energized. – Two Full Bridges ON at the same time (Fig. 16) in which two loads at the same time are energized.
L6205 Figure 17. Mounting the PowerSO package. Slug soldered to PCB with dissipating area Slug soldered to PCB with dissipating area plus ground layer Slug soldered to PCB with dissipating area plus ground layer contacted through via holes Figure 18. PowerSO20 Junction-Ambient thermal resistance versus on-board copper area.
L6205 Figure 21. Typical Quiescent Current vs. Supply Voltage Figure 24. Typical High-Side RDS(ON) vs. Supply Voltage Iq [m A] RDS(ON) [Ω] 5.6 fsw = 1kHz 0.380 Tj = 25°C 0.376 Tj = 85°C 5.4 0.372 Tj = 25°C 0.368 Tj = 125°C 0.364 5.2 0.360 0.356 5.0 0.352 0.348 4.8 0.344 0.340 0.336 4.6 0 10 20 30 V S [V] 40 50 0 60 5 10 15 20 25 30 VS [V] Figure 22. Normalized Typical Quiescent Current vs. Switching Frequency Figure 25. Normalized RDS(ON) vs.
L6205 DIM. mm MIN. TYP. A a1 inch MAX. MIN. TYP. 3.6 0.1 0.142 0.3 a2 0.004 0.012 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 0.013 c 0.23 0.32 0.009 D (1) 15.8 16 0.622 0.630 D1 9.4 9.8 0.370 0.386 E 13.9 14.5 0.547 0.570 e 1.27 e3 11.43 E1 (1) 10.9 0.450 0.429 0.437 2.9 0.114 E3 5.8 6.2 0.228 0.244 G 0 0.1 0.000 0.004 H 15.5 15.9 0.610 h L 0.626 1.1 0.8 JEDEC MO-166 0.043 1.1 N Weight: 1.9gr 0.050 11.
L6205 mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 D 0.015 0.020 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 F 7.10 0.280 I 5.10 0.201 L OUTLINE AND MECHANICAL DATA 3.30 0.130 Powerdip 20 Z 1.27 0.
L6205 mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 SO20 K 0˚ (min.)8˚ (max.
L6205 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.
