L6599A Improved high-voltage resonant controller Datasheet - production data Applications LCD and PDP TV Desktop PC, entry-level server Telecom SMPS DIP16 SO16N High efficiency industrial SMPS AC-DC adapter, open frame SMPS Features Table 1.
Contents L6599A Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Absolute maximum ratings .
L6599A 1 Description Description The L6599A is an improved revision of the previous L6599. It is a double-ended controller specific to series-resonant half bridge topology. It provides 50% complementary duty cycle: the high-side switch and the low-side switch are driven ON/OFF 180° out-of-phase for exactly the same time. Output voltage regulation is obtained by modulating the operating frequency.
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L6599A 3 Pin connection Pin connection Figure 2. Pin connection (top view) &VV 9%227 '(/$< +9* &) 287 5)PLQ 1 & 67%< 9FF ,6(1 /9* /,1( *1' ',6 3)&B6723 $0 Y Table 2. Pin description Pin no. 1 2 3 4 Type Function Css Soft-start.
Pin connection L6599A Table 2. Pin description (continued) Pin no. 5 6 7 8 6/37 Type Function STBY Burst mode operation threshold. The pin senses some voltage related to the feedback control, which is compared to an internal reference (1.24 V). If the voltage on the pin is lower than the reference, the IC enters an idle state and its quiescent current is reduced. The chip restarts switching as the voltage exceeds the reference by 50 mV. Soft-start is not invoked.
L6599A Pin connection Table 2. Pin description (continued) Pin no. Type Function 11 LVG Low-side gate-drive output. The driver is capable of 0.3 A min. source and 0.8 A min. sink peak current to drive the lower MOSFET of the half bridge leg. The pin is actively pulled to GND during UVLO. 12 Vcc Supply voltage of both the signal part of the IC and the low-side gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be useful to get a clean bias voltage for the signal part of the IC.
Electrical data L6599A 4 Electrical data 4.1 Absolute maximum ratings Table 3. Absolute maximum rating Symbol Pin Parameter Value Unit VBOOT 16 Floating supply voltage -1 to 618 V HVG 15 HVG voltage VOUT -0.3 to VBOOT +0.3 V VOUT 14 Floating ground voltage -3 up to a value included in the range VBOOT -18 and VBOOT V dVOUT /dt 14 Floating ground max. slew rate 50 V/ns Vcc 12 IC supply voltage (Icc = 25 mA) Self-limited V LVG 11 LVG voltage -0.3 to VCC +0.
L6599A 5 Electrical characteristics Electrical characteristics TJ = 0 to 105 °C, Vcc = 15 V, VBOOT = 15 V, CHVG = CLVG = 1 nF; CF = 470 pF; RRFmin = 12 k; unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit 8.85 - 16 V IC supply voltage Vcc Operating range After device turn-on VccOn Turn-on threshold Voltage rising 10 10.7 11.4 V VccOff Turn-off threshold Voltage falling 7.45 8.15 8.
Electrical characteristics L6599A Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit - - -1 µA 1.78 1.85 1.92 V 48 50 52 % - 58.2 60 61.8 RRFmin = 2.7 k 240 250 260 0.2 0.3 0.4 µs DIS function IDIS Vth Input bias current VDIS = 0 to Vth rising(1) Disable threshold Voltage Output duty cycle Both HVG and LVG Oscillator D fosc Oscillation frequency TD Deadtime Between HVG and LVG VCFp Peak value - - 3.
L6599A Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit 1.5 V Low-side gate driver (voltages referred to GND) VLVGL Output low voltage Isink = 200 mA - - VLVGH Output high voltage Isource = 5 mA 12.8 13.3 Isourcepk Peak source current - -0.3 - - A Peak sink current - 0.
Typical electrical performance 6 L6599A Typical electrical performance Figure 3. Device consumption vs. supply voltage Figure 4. IC consumption vs. junction temperature AM13167v1 Figure 5. VCC clamp voltage vs. junction temperature AM13168v1 Figure 6. UVLO thresholds vs.
L6599A Typical electrical performance Figure 7. Oscillator frequency vs. junction temperature Figure 8. Deadtime vs. junction temperature AM13172v1 AM13171v1 Figure 9. Oscillator frequency vs. timing components Figure 10. Oscillator ramp vs. junction temperature Pin 3 fsw [kHz] 1000 Vcc = 15V CF: 220 pF 100 330 pF 470 pF 680 pF 1.0 nF 2.2 nF 10 0 5 10 15 20 RFmin [kΩ ] AM13174v AM13173v1 Figure 11. Reference voltage vs. junction temperature Figure 12. Current mirroring ratio vs.
Typical electrical performance L6599A Figure 13. OCP delay source current vs. junction temperature Figure 14. OCP delay thresholds vs. junction temperature AM13178v1 AM13177v1 Figure 15. Standby thresholds vs. junction temperature Figure 16. Current sense thresholds vs. junction temperature AM13180v1 AM13179v1 Figure 17. Line thresholds vs. junction temperature Figure 18. Line source current vs. junction temperature Pin 7 (uA) 13.5 Vcc = 15V 13 12.5 12 11.
L6599A Typical electrical performance Figure 19. Latched disable threshold vs.
Application information 7 L6599A Application information The L6599A is an advanced double-ended controller specific for resonant half bridge topology (see Figure 21). In these converters the switches (MOSFETs) of the half bridge leg are alternately switched on and off (180° out-of-phase) for exactly the same time.
L6599A Application information Figure 21. Typical system block diagram 3)& 35( 5(*8/$725 237,21$/ 5(621$17 +$/) %5,'*( 9RXWGF 9LQDF 5HVRQDQW +% LV WXUQHG RII LQ FDVH RI 3)& V DQRPDORXV RSHUDWLRQ IRU VDIHW\ / / $ / 6 / + '$3 / / '$3 $ '$3 / $ 3)& FDQ EH WXUQHG RII DW OLJKW ORDG WR HDVH FRPSOLDQFH ZLWK HQHUJ\ VDYLQJ UHJXODWLRQV $0 Y 7.
Application information L6599A Figure 22. Oscillator internal block diagram / $ 9 .0ā,5 5)PLQ 5)PLQ 5VV 5)PD[ ā.0ā,5 ,5 9 &VV .
L6599A Application information Figure 23. Oscillator waveforms and their relationship with gate-driving signals &) +9* 7' 7' W /9* W +% W W $0 Y In Figure 23 the timing relationship between the oscillator waveform and the gate-drive signal, as well as the swinging node of the half bridge leg (HB), is shown. Note that the lowside gate drive is turned on while the oscillator triangle is ramping up and the high-side gate drive is turned on while the triangle is ramping down.
Application information L6599A Figure 24. Burst mode implementation: a) narrow input voltage range; b) wide input voltage range % 5)PLQ 5)PLQ 5)PLQ 5)PD[ 67%< / $ '$3 5)PLQ 5' '$3 / $ 5)PD[ 67%< /,1( 5$ 5& 5% 5$ 5% !! 5& D E $0 Y Essentially, RFmax defines the switching frequency fmax above which the L6599A enters burst mode operation.
L6599A Application information the no load consumption of this stage (0.5 1 W). There is no compliance issue in that, because EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is envisaged when the converter operates with light or no load. To do so, the L6599A provides pin 9 (PFC_STOP): it is an open collector output, normally open, that is asserted low when the IC is idle during burst mode operation.
Application information 7.3 L6599A Soft-start Generally speaking, the purpose of soft-start is to progressively increase converter power capability when it is started up, so as to avoid excessive inrush current. In resonant converters the deliverable power depends inversely on frequency, soft-start is then done by sweeping the operating frequency from an initial high value until the control loop takes over.
L6599A Application information Typically, RSS and CSS are selected based on the following relationships: Equation 5 R SS RFmin 3 10 3 ; CSS fstart R SS 1 fmin where fstart is recommended to be at least 4 times fmin. The proposed criterion for CSS is quite empirical and is a compromise between an effective soft-start action and an effective OCP (see next section). Please refer to the timing diagram of Figure 27 to see some significant signals during the soft-start phase. 7.
Application information L6599A Figure 28. Current sensing techniques: a) with sense resistor, b) “lossless”, with capacitive shunt W | 9&USN IPLQ &U ,6(1 '$3 / $ ,6(1 , &U W | IPLQ 5V 1 &$ 5$ '$3 / $ 9VSN 5% &% D 1 , &U &U E $0 Y The L6599A is equipped with a current sensing input (pin 6, ISEN) and a sophisticated overcurrent management system.
L6599A Application information The circuit shown in Figure 28b can be operated in two different ways. If the resistor RA in series to CA is small (not above some hundred , just to limit current spiking), the circuit operates like a capacitive current divider; CA is typically selected equal to Cr/100 or less and is a low-loss type, the sense resistor RB is selected as: Equation 7 RB C 0 .8 1 r ICrpkx C A and CB is such that RB·CB is in the range of 10 /fmin.
Application information L6599A Figure 29. Soft-start and delayed shutdown upon overcurrent timing diagram 9FF 76+ &VV 3ULPDU\ &XUUHQW ,6(1 '(/$< 9 703 76723 W 7VV W $ 9 W 9 W 9 9 W 9RXW W 3)&B6723 67$57 83 62)7 67$57 1250$/ 23(5$7,21 29(5 /2$' 1250$/ 23(5$7,21 29(5/2$' 6+87'2:1 62)7 67$57 W 0,1 32:(5 $0 Y This function is realized with pin 2 (DELAY), by means of a capacitor CDelay and a parallel resistor RDelay connected to ground.
L6599A Application information The timing diagram of Figure 29 shows this operation. Note that, if, during TSTOP, the supply voltage of the L6599A (Vcc) falls below the UVLO threshold, the IC records the event and does not restart immediately after Vcc exceeds the startup threshold if V(DELAY) is still higher than 0.3 V. Also the PFC_STOP pin stays low as long as V(DELAY) is greater than 0.3 V.
Application information L6599A Figure 30. Line sensing function: internal block diagram and timing diagram +9 ,QSXW EXV 9LQ21 9LQ2)) W /,1( 9 +9 ,QSXW EXV W 9FF 9LQ2. W ,+<6 5+ $ /,1( 5/ $ 9 9LQ2. W 9FF 9 W / $ /9* +9* 9RXW W W $0 Y With reference to Figure 28, the following relationships can be established for the ON (VinON) and OFF (VinOFF) thresholds of the input voltage: Equation 11 Vin ON 1.24 1.24 13 10 6 RH RL Vin OFF 1.
L6599A Application information kind. If the function is not used, the pin must be connected to a voltage greater than 1.24 V but lower than 6 V (worst-case value of the 7 V threshold). 7.7 Bootstrap section The supply of the floating high-side section is obtained by means of a bootstrap circuitry. This solution normally requires a high-voltage fast recovery diode (DBOOT, Figure 31a) to charge the bootstrap capacitor CBOOT. In the L6599A a patented integrated structure, replaces this external diode.
Application information L6599A Equation 13 VDrop Ich arg eR(DS)on VF Qg Tch arg e R(DS )on VF where Qg is the gate charge of the external Power MOSFET, R(DS)ON is the on-resistance of the bootstrap DMOS (150 W, typ.) and Tcharge is the ON-time of the bootstrap driver, which equals about half the switching period minus the deadtime TD.
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Package information 8 L6599A Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark.
L6599A 8.1 Package information DIP16 package information Figure 33. DIP16 package outline Table 6. DIP16 package mechanical data Symbol Dimensions (mm) Min. Typ. Max. a1 0.51 - - B 0.77 - 1.65 b - 0.5 - b1 - 0.25 - D - - 20 E - 8.5 - e - 2.54 - e3 - 17.78 - F - - 7.1 I - - 5.1 L - 3.3 - Z - - 1.
Package information 8.2 L6599A SO16N package information Figure 34.
L6599A Package information Table 7. SO16N package mechanical data Symbol Dimensions (mm) Min. Typ. Max. A - - 1.75 A1 0.10 - 0.25 A2 1.25 - - b 0.31 - 0.51 c 0.17 - 0.25 D 9.80 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e - 1.27 - h 0.25 - 0.50 L 0.40 - 1.27 k 0 - 8° ccc - - 0.10 Figure 35.
Revision history 9 L6599A Revision history Table 8. Document revision history 36/37 Date Revision Changes 19-Jan-2009 1 Initial release 25-Feb-2009 2 Updated Table 5 on page 11 13-Mar-2009 3 Updated data on Table 5 on page 11 under oscillator section 30-Oct-2009 4 Updated Table 5 on page 11 28-Sep-2010 5 Added: Section 6 on page 14 10-Sep-2012 6 Updated Figure 9: Oscillator frequency vs.
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