LIS2DH MEMS digital output motion sensor: ultra low-power high performance 3-axis “femto” accelerometer Features ■ Wide supply voltage, 1.71 V to 3.6 V ■ Independent IOs supply (1.
Contents LIS2DH Contents 1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Mechanical characteristics . . . . . . . . . . . . . . .
LIS2DH 5 Contents 4.1.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1.3 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1.4 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1.5 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Digital interfaces . . . . . . . . . . . . . . . .
Contents LIS2DH 7.20 INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.21 INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.22 INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.23 INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.24 INT2_SRC (35h) . . . . . . . . . . . . . .
LIS2DH List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48.
List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. 6/49 LIS2DH INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIS2DH List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
Block diagram and pin description LIS2DH 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram X+ CHARGE AMPLIFIER Y+ Z+ a CS A/D CONVERTER MUX I2C CONTROL LOGIC SCL/SPC SDA/SDO/SDI SPI Z- SDO/SA0 YX- TRIMMING CIRCUITS Temperature Sensor SELF TEST CONTROL LOGIC & INTERRUPT GEN. 32 Level FIFO CLOCK INT 1 INT 2 AM10218V1 Pin description Pin connection Res Z 12 GND 1 Res Figure 2. Res 1.
LIS2DH Block diagram and pin description Table 2.
Mechanical and electrical specifications LIS2DH 2 Mechanical and electrical specifications 2.1 Mechanical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted(a) Table 3. Symbol FS So Mechanical characteristics Parameter Measurement range(2) Sensitivity Test conditions Min. Typ.(1) FS bit set to 00 ±2.0 FS bit set to 01 ±4.0 FS bit set to 10 ±8.0 FS bit set to 11 ±16.
LIS2DH Table 3. Symbol TCOff Vst Top Mechanical and electrical specifications Mechanical characteristics (continued) Parameter Test conditions Zero-g level change vs temperature Min. Typ.(1) Max delta from 25 °C Max. Unit mg/°C ±0.5 FS bit set to 00 X axis; Normal mode 17 360 LSb FS bit set to 00 Self-test output change(5),(6),(7) Y axis; Normal mode 17 360 LSb FS bit set to 00 Z axis; Normal mode 17 360 LSb -40 +85 °C Operating temperature range 1.
Mechanical and electrical specifications 2.3 LIS2DH Electrical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted(c) Table 5. Electrical characteristics Symbol Vdd Vdd_IO Parameter Test conditions Supply voltage (2) I/O pins supply voltage Min. Typ.(1) Max. Unit 1.71 2.5 3.6 V Vdd+0.1 V 1.
LIS2DH Mechanical and electrical specifications 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 6.
Mechanical and electrical specifications 2.4.2 LIS2DH I2C - Inter IC control interface Subject to general operating conditions for Vdd and top. Table 7. I2C slave timing values I2C standard mode (1) Symbol I2C fast mode (1) Parameter f(SCL) Unit SCL clock frequency Min Max Min Max 0 100 0 400 tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time kHz µs 0 ns 3.45 0.01 0.
LIS2DH 2.5 Mechanical and electrical specifications Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 8. Absolute maximum ratings Symbol Vdd Vdd_IO Vin Ratings Maximum value Unit Supply voltage -0.3 to 4.
Mechanical and electrical specifications 2.6 LIS2DH Terminology and functionality Terminology 2.6.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again.
LIS2DH Mechanical and electrical specifications The turn-on time to change from all operating mode is reported into Table 10.: Turn-on time for operating mode change. Table 10. Turn-on time for operating mode change Turn-on Tim Operating mode change 12-bit mode to 8 bit mode 1/ODR 12-bit mode to 10 bit mode 1/ODR 10-bit mode to 8 bit mode 1/ODR 10-bit mode to 12 bit mode 7/ODR 8-bit mode to 10 bit mode 1/ODR 8-bit mode to 12 bit mode 7/ODR Table 11.
Mechanical and electrical specifications 2.6.5 LIS2DH 6D / 4D orientation detection The LIS2DH include 6D / 4D orientation detection. 6D / 4D orientation recognition In this configuration the interrupt is generated when the device is stable in a known direction. In 4D configuration Z axis position detection is disable. 2.6.6 “Sleep to wake” and “Return to sleep” The LIS2DH can be programmed to automatically switch to Low power mode upon recognition of a determined event.
LIS2DH Mechanical and electrical specifications The LIS2DH may also be configured to generate an inertial Wake-Up and Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both FreeFall and Wake-Up can be available simultaneously on two different pins. 2.9 Factory calibration The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff). The trimming values are stored inside the device in a non volatile memory.
Application hints 3 LIS2DH Application hints Figure 5. LIS2DH electrical connection Vdd_IO Vdd GND Pin 1 indicator 14 12 SCL/SPC 11 1 GND SDA/SDI/SDO GND SDO/SA0 GND CS 4 8 10µF Vdd 100nF 7 5 Vdd_IO INT1 INT2 GND Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO AM10220V1 The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line.
LIS2DH Digital main blocks 4 Digital main blocks 4.1 FIFO The LIS2DH embeds a 32-slot data FIFO for each of the three output channels, X, Y and Z. This allows a consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wakeup only when needed and burst the significant data out from the FIFO. This buffer can work accordingly to four different modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode.
Digital main blocks LIS2DH The reading address is automatically updated by the device and it rolls back to 0x28 when register 0x2D is reached. In order to read all FIFO levels in a multiple byte reading,192 bytes (6 output registers by 32 levels) have to be read.
LIS2DH 5 Digital interfaces Digital interfaces The registers embedded inside the LIS2DH may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS line must be tied high (i.e. connected to Vdd_IO). Table 12.
Digital interfaces 5.1.1 LIS2DH I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy.
LIS2DH Digital interfaces Table 16. Master Transfer when master is writing multiple bytes to slave: ST SAD + W Slave SAK Table 17. Master Master Slave ST DATA DATA SAK SAK SP SAK Transfer when master is receiving (reading) one byte of data from slave: ST SAD + W Slave Table 18.
Digital interfaces LIS2DH Figure 6. Read and write protocol CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 AM10129V1 CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission).
LIS2DH 5.2.1 Digital interfaces SPI read Figure 7. SPI read protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 AM10130V1 The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0).
Digital interfaces 5.2.2 LIS2DH SPI write Figure 9. SPI write protocol CS SPC SDI D I7 D I6 D I5 D I4 DI3 DI2 DI1 DI0 RW MS AD5 AD 4 AD 3 AD2 AD 1 AD0 AM10132V1 The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0).
LIS2DH Digital interfaces Figure 11. SPI read protocol in 3-wires mode CS SPC SDI/O D O7 D O6 D O5 DO4 DO3 DO2 DO1 DO0 RW MS AD5 AD 4 AD 3 AD2 AD1 AD 0 AM10134V1 The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode).
Register mapping 6 LIS2DH Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 19.
LIS2DH Register mapping Table 19.
Registers Description LIS2DH 7 Registers Description 7.1 STATUS_AUX (07h) Table 20. -- Table 21. 7.2 STATUS_REG_AUX register TOR -- -- -- TDA -- -- STATUS_REG_AUX description TOR Temperature Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new temperature data has overwritten the previous one) TDA Temperature new Data Available.
LIS2DH Registers Description Table 25. TEMP_CFG_REG description TEMP_EN[1-0] 7.6 Temperature sensor (T) enable. Default value: 00 (00: T disabled; 11: T enabled) CTRL_REG1 (20h) Table 26. CTRL_REG1 register ODR3 Table 27. ODR2 ODR1 ODR0 LPen Zen Yen Xen CTRL_REG1 description ODR3-0 Data rate selection. Default value: 00 (0000:Power Down mode; Others: Refer to Table 28, "Data Rate Configuration") LPen Low power mode enable.
Registers Description 7.7 LIS2DH CTRL_REG2 (21h) Table 29. CTRL_REG2 register HPM1 HPM0 Table 30. FDS HPCLICK HPIS2 HPIS1 High Pass filter Mode Selection. Default value: 00 Refer to Table 31, "High pass filter mode configuration" HPCF2 HPCF1 High Pass filter Cut Off frequency selection FDS Filtered Data Selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register and FIFO) HPCLICK High Pass filter enabled for CLICK function.
LIS2DH Registers Description Table 33. 7.9 CTRL_REG3 description (continued) I1_AOI2 AOI2 interrupt on INT1 pin. Default value 0. (0: Disable; 1: Enable) I1_DRDY1 DRDY1 interrupt on INT1 pin. Default value 0. (0: Disable; 1: Enable) I1_DRDY2 DRDY2 interrupt on INT1 pin. Default value 0. (0: Disable; 1: Enable) I1_WTM FIFO Watermark interrupt on INT1 pin. Default value 0. (0: Disable; 1: Enable) I1_OVERRUN FIFO Overrun interrupt on INT1 pin. Default value 0.
Registers Description 7.10 CTRL_REG5 (24h) Table 37. BOOT Table 38. 7.11 LIS2DH CTRL_REG5 register FIFO_EN -- LIR_INT1 D4D_INT1 LIR_INT2 D4D_INT2 CTRL_REG5 description BOOT Reboot memory content. Default value: 0 (0: Normal mode; 1: reboot memory content) FIFO_EN FIFO enable. Default value: 0 (0: FIFO disable; 1: FIFO Enable) LIR_INT1 Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by reading INT1_SRC itself. Default value: 0.
LIS2DH 7.12 Registers Description REFERENCE/DATACAPTURE (26h) Table 41. Ref7 Table 42. REFERENCE register Ref6 Ref3 Ref2 Ref1 Ref0 Reference value for Interrupt generation. Default value: 0 STATUS_REG (27h) Table 43. ZYXOR Table 44. 7.14 Ref4 REFERENCE register description Ref 7-Ref0 7.13 Ref5 STATUS register ZOR YOR XOR ZYXDA ZDA YDA XDA STATUS register description ZYXOR X, Y and Z axis Data Overrun.
Registers Description 7.15 LIS2DH OUT_Y_L (2Ah), OUT_Y_H (2Bh) Y-axis acceleration data. The value is expressed as two’s complement left justified. Please refer to Section 2.6.3: High resolution, Normal mode, Low power mode. 7.16 OUT_Z_L (2Ch), OUT_Z_H (2Dh) Z-axis acceleration data. The value is expressed as two’s complement left justified. Please refer to Section 2.6.3: High resolution, Normal mode, Low power mode. 7.17 FIFO_CTRL_REG (2Eh) Table 45. FM1 FIFO_CTRL_REG register FM0 Table 46.
LIS2DH 7.19 Registers Description INT1_CFG (30h) Table 49. AOI INT1_CFG register 6D Table 50. ZHIE/ ZUPE ZLIE/ ZDOWNE YHIE/ YUPE YLIE/ YDOWNE XHIE/ XUPE XLIE/ XDOWNE INT1_CFG description AOI And/Or combination of Interrupt events. Default value: 0. Refer to Table 51, "Interrupt mode" 6D 6 direction detection function enabled. Default value: 0. Refer to Table 51, "Interrupt mode" ZHIE/ ZUPE Enable interrupt generation on Z high event or on Direction recognition.
Registers Description 7.20 LIS2DH INT1_SRC (31h) Table 52. INT1_SRC register 0 Table 53. IA ZH ZL YH YL XH XL INT1_SRC description IA Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) ZH Z high. Default value: 0 (0: no interrupt, 1: Z High event has occurred) ZL Z low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) YH Y high. Default value: 0 (0: no interrupt, 1: Y High event has occurred) YL Y low.
LIS2DH 7.22 Registers Description INT1_DURATION (33h) Table 56. 0 Table 57. D6 - D0 INT1_DURATION register D6 D5 D4 D3 D2 D1 D0 INT1_DURATION description Duration value. Default value: 000 0000 1 LSb = 1/ODR D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration steps and maximum values depend on the ODR chosen. Duration time is measured in N/ODR, where N is the content of the duration register. 7.23 INT2_CFG (34h) Table 58. AOI Table 59.
Registers Description Table 59. LIS2DH INT2_CFG description (continued) XHIE Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) XLIE Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Content of this register is loaded at boot.
LIS2DH Registers Description Table 62. INT2_SRC description (continued) YL Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred) XH X high. Default value: 0 (0: no interrupt, 1: X high event has occurred) XL X Low. Default value: 0 (0: no interrupt, 1: X low event has occurred) Interrupt 2 source register. Read only register.
Registers Description 7.27 CLICK_CFG (38h) Table 67. -- Table 68. 7.28 LIS2DH CLICK_CFG register -- ZS YD YS XD XS CLICK_CFG description ZD Enable interrupt double tap-tap on Z axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ZS Enable interrupt single tap-tap on Z axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel.
LIS2DH Registers Description Table 70. 7.29 CLICK_SRC description (continued) Y Y Click-Click detection. Default value: 0 (0: no interrupt, 1: Y High event has occurred) X X Click-Click detection. Default value: 0 (0: no interrupt, 1: X High event has occurred) CLICK_THS (3Ah) Table 71. - Table 72. CLICK_THS register Ths6 - Table 74. Ths2 Ths1 Ths0 TLI1 TLI0 TLA1 TLA0 TW1 TW0 Click-Click threshold.
Registers Description Table 78. TW7-TW0 7.33 -- Table 80. Acth[6-0] Click-Click Time Window TIME_WINDOW register Acth6 Acth5 Acth4 Acth3 Acth2 Acth1 Acth0 TIME_WINDOW description Sleep to wake, return to Sleep activation threshold in Low power mode 1LSb = 16mg @FS=2g 1LSb = 32 mg @FS=4g 1LSb = 62 mg @FS=8g 1LSb = 186 mg @FS=16g Act_DUR (3Fh) Table 81. ActD7 Table 82. ActD[7-0] 46/49 TIME_WINDOW description Act_THS(3Eh) Table 79. 7.
LIS2DH 8 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 83. LGA-14 2x2x1 mechanical dimensions Ref. Min. Typ. A1 Max. 1 A2 0.785 A3 0.200 D1 1.850 2.000 2.150 E1 1.850 2.000 2.150 L1 0.900 L2 1.
Revision history 9 LIS2DH Revision history Table 84. 48/49 Document revision history Date Revision 25-Nov-2011 1 Changes Initial release.
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