Datasheet

ManualsBrandsST ManualsIntegrated Circuits (ICs)Acceleration Sensor, Digital, 12bit, LGA

This is information on a product in full production.

December 2016 DocID17530 Rev 2 1/54

LIS3DH

MEMS digital output motion sensor:

ultra-low-power high-performance 3-axis "nano" accelerometer

Datasheet - production data

Features

 Wide supply voltage, 1.71 V to 3.6 V

 Independent IO supply (1.8 V) and supply

voltage compatible

 Ultra-low-power mode consumption

down to 2 μA

2g/±4g/8g/16g dynamically selectable full

scale

 I

C/SPI digital output interface

 16-bit data output

 2 independent programmable interrupt

generators for free-fall and motion detection

 6D/4D orientation detection

 Free-fall detection

 Motion detection

 Embedded temperature sensor

 Embedded self-test

 Embedded 32 levels of 16-bit data output FIFO

 10000 g high shock survivability

 ECOPACK

, RoHS and “Green” compliant

Applications

 Motion activated functions

 Free-fall detection

 Click/double-click recognition

 Intelligent power saving for handheld devices

 Pedometers

 Display orientation

 Gaming and virtual reality input devices

 Impact recognition and logging

 Vibration monitoring and compensation

Description

The LIS3DH is an ultra-low-power high-

performance three-axis linear accelerometer

belonging to the “nano” family, with digital I

C/SPI

serial interface standard output. The device

features ultra-low-power operational modes that

allow advanced power saving and smart

embedded functions.

The LIS3DH has dynamically user-selectable full

scales of 2g/±4g/8g/16g and is capable of

measuring accelerations with output data rates

from 1 Hz to 5.3 kHz. The self-test capability

allows the user to check the functioning of the

sensor in the final application. The device may be

configured to generate interrupt signals using two

independent inertial wake-up/free-fall events as

well as by the position of the device itself.

Thresholds and timing of interrupt generators are

programmable by the end user on the fly. The

LIS3DH has an integrated 32-level first-in, first-

out (FIFO) buffer allowing the user to store data in

order to limit intervention by the host processor.

The LIS3DH is available in small thin plastic land

grid array package (LGA) and is guaranteed to

operate over an extended temperature range

from -40 °C to +85 °C.

/*$[[PP

Table 1. Device summary

Order codes

Temp.

range [C]

Package Packaging

LIS3DHTR -40 to +85 LGA-16 Tape and reel

www.st.com

Summary of content (54 pages)

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LIS3DH MEMS digital output motion sensor: ultra-low-power high-performance 3-axis "nano" accelerometer Datasheet - production data  Display orientation  Gaming and virtual reality input devices  Impact recognition and logging  Vibration monitoring and compensation Description /*$ [ [ PP Features  Wide supply voltage, 1.71 V to 3.6 V  Independent IO supply (1.
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Contents LIS3DH Contents 1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Mechanical characteristics . . . . . . . . . . . . . . . .
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LIS3DH 6 Contents 5.1.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.3 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.4 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.5 Retrieving data from FIFO . . . . . .
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Contents 9 10 4/54 LIS3DH 8.19 FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.20 FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.21 INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.22 INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.23 INT1_THS (32h) . . . . . . . . . . . . .
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LIS3DH List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48.
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. 6/54 LIS3DH REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . .
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LIS3DH List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI slave timing diagram . . . . . . . . . .
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Block diagram and pin description LIS3DH 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram ; < &+$5*( $03/,),(5 = D $ ' &219(57(5 08; &6 = < , & &21752/ /2*,& ; 6&/ 63& 6'$ 6'2 6', 63, $'& $'& ,QSXW 6'2 6$ $'& $'& ,QSXW $ ' &219(57(5 $'& $'& ,QSXW 7(03(5$785( 6(1625 6(/) 7(67 1.2 5()(5(1&( 75,00,1* &,5&8,76 /HYHO ),)2 &/2&. &21752/ /2*,& ,17 ,17(55837 *(1 ,17 Pin description Figure 2.
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LIS3DH Block diagram and pin description Table 2.
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Mechanical and electrical specifications LIS3DH 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Vdd = 2.5 V, T = 25 °C unless otherwise noted (a) Table 4. Mechanical characteristics Symbol FS So Parameter Measurement range(2) Sensitivity Test conditions Min. Typ.(1) FS bit set to 00 ±2.0 FS bit set to 01 ±4.0 FS bit set to 10 ±8.0 FS bit set to 11 ±16.
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LIS3DH Mechanical and electrical specifications Table 4. Mechanical characteristics Symbol TCOff An Vst Top Parameter Test conditions Min. Typ.(1) Max. Unit Zero-g level change vs temperature Max delta from 25 °C ±0.
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Mechanical and electrical specifications 2.2 LIS3DH Temperature sensor characteristics Vdd = 2.5 V, T = 25 °C unless otherwise noted (b) Table 5. Temperature sensor characteristics Symbol Parameter Test condition TSDr Temperature sensor output change vs temperature TODR Temperature refresh rate Top Operating temperature range Min. Typ.(1) Max. Unit 1 digit/°C(2) ODR Hz -40 +85 °C 1. Typical specifications are not guaranteed. 2. 8-bit resolution. 2.
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LIS3DH Mechanical and electrical specifications 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 7.
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Mechanical and electrical specifications 2.4.2 LIS3DH I2C - Inter IC control interface Subject to general operating conditions for Vdd and top. Table 8. I2C slave timing values Symbol f(SCL) I2C standard Parameter SCL clock frequency I2C fast mode (1) Min Max Min Max 0 100 0 400 tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0 th(ST) START condition hold time 4 0.
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LIS3DH 2.5 Mechanical and electrical specifications Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 9. Absolute maximum ratings Symbol Vdd Vdd_IO Vin Note: Ratings Maximum value Unit Supply voltage -0.3 to 4.
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Terminology and functionality LIS3DH 3 Terminology and functionality 3.1 Terminology 3.1.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined, for example, by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again.
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LIS3DH Terminology and functionality The turn-on time to transition to another operating mode is given in Table 11. Table 11. Turn-on time for operating mode transition Turn-on time Operating mode change [ms] 12-bit mode to 8-bit mode 1/ODR 12-bit mode to 10-bit mode 1/ODR 10-bit mode to 8-bit mode 1/ODR 10-bit mode to 12-bit mode 7/ODR 8-bit mode to 10-bit mode 1/ODR 8-bit mode to 12-bit mode 7/ODR Table 12. Current consumption of operating modes Operating mode [Hz] 3.2.
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Terminology and functionality 3.2.3 LIS3DH 6D / 4D orientation detection The LIS3DH provides the capability to detect the orientation of the device in space, enabling easy implementation of energy-saving procedures and automatic image rotation for mobile devices. The 4D detection is a subset of the 6D function especially defined to be implemented in mobile devices for portrait and landscape computation. In 4D configuration, the Z-axis position detection is disabled. 3.2.
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LIS3DH Terminology and functionality The LIS3DH features a Data-Ready signal (DRDY) which indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device. The LIS3DH may also be configured to generate an inertial wake-up and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both freefall and wake-up can be available simultaneously on two different pins. 3.
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Application hints 4 LIS3DH Application hints Figure 5. LIS3DH electrical connections $'& $'& 9GG ) 9GGB,2 $'& 723 9,(: ,17 Q) ,17 9GGB,2 5SX Nȍ &6 5SX Nȍ 6'2 6$ 6'$ 6', 6'2 6&/ 63& 3XOO XS WR EH DGGHG ZKHQ , & LQWHUIDFH LV XVHG *1' 'LJLWDO VLJQDO IURP WR VLJQDO FRQWUROOHU 6LJQDO OHYHOV DUH GHILQHG E\ SURSHU VHOHFWLRQ RI 9GGB,2 The device core is supplied through the Vdd line while the I/O pads are supplied through the Vdd_IO line.
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LIS3DH Application hints Table 13.
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Digital main blocks LIS3DH 5 Digital main blocks 5.1 FIFO The LIS3DH embeds a 32-level FIFO for each of the three output channels, X, Y and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. In order to enable the FIFO buffer, the FIFO_EN bit in CTRL_REG5 (24h) must be set to ‘1’.
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LIS3DH 5.1.3 Digital main blocks Stream mode In Stream mode the FIFO continues filling data from the X, Y, and Z accelerometer channels until the buffer is full (a set of 32 samples stored) at which point the FIFO buffer index restarts from the beginning and older data is replaced by the current data. The oldest values continue to be overwritten until a read operation frees the FIFO slots.
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Digital interfaces 6 LIS3DH Digital interfaces The registers embedded inside the LIS3DH may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, the CS line must be tied high (i.e. connected to Vdd_IO). Table 14. Serial interface pin description Pin name CS 6.
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LIS3DH 6.1.1 Digital interfaces I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy.
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Digital interfaces LIS3DH Table 19. Transfer when master is receiving (reading) one byte of data from slave Master ST SAD + W Slave SUB SAK SR SAD + R SAK NMAK SAK SP DATA Table 20. Transfer when master is receiving (reading) multiple bytes of data from slave Master ST SAD+W Slave SUB SAK SR SAD+R SAK MAK SAK DATA MAK DATA NMAK SP DATA Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited.
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LIS3DH 6.2 Digital interfaces SPI bus interface The LIS3DH SPI is a bus slave. The SPI allows writing to and reading from the registers of the device. The serial interface interacts with the application using 4 wires: CS, SPC, SDI and SDO. Figure 6. Read and write protocol &6 63& 6', 5: ', ', ', ', ', ', ', ', 06 $' $' $' $' $' $' 6'2 '2 '2 '2 '2 '2 '2 '2 '2 CS is the serial port enable and it is controlled by the SPI master.
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Digital interfaces 6.2.1 LIS3DH SPI read Figure 7. SPI read protocol &6 63& 6', 5: 06 $' $' $' $' $' $' 6'2 '2 '2 '2 '2 '2 '2 '2 '2 The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0, does not increment the address; when 1, increments the address in multiple reads. bit 2-7: address AD(5:0).
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LIS3DH 6.2.2 Digital interfaces SPI write Figure 9. SPI write protocol &6 63& 6', ', ', ', ', ', ', ', ', 5: 06 $' $' $' $' $' $' The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0, does not increment the address; when 1, increments the address in multiple writes. bit 2 -7: address AD(5:0).
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Digital interfaces 6.2.3 LIS3DH SPI read in 3-wire mode 3-wire mode is entered by setting the bit SIM (SPI serial interface mode selection) to ‘1’ in CTRL_REG4 (23h). Figure 11. SPI read protocol in 3-wire mode &6 63& 6', 2 '2 '2 '2 '2 '2 '2 '2 '2 5: 06 $' $' $' $' $' $' The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0, does not increment the address; when 1, increments the address in multiple reads. bit 2-7: address AD(5:0).
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LIS3DH 7 Register mapping Register mapping The table given below provides a list of the 8-bit registers embedded in the device and the corresponding addresses. Table 21.
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Register mapping LIS3DH Table 21.
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LIS3DH Registers description 8 Registers description 8.1 STATUS_REG_AUX (07h) Table 22. STATUS_REG_AUX register 321OR 3OR 2OR 1OR 321DA 3DA 2DA 1DA Table 23. STATUS_REG_AUX description 8.2 321OR 1, 2 and 3-axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous set) 3OR 3-axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the 3-axis has overwritten the previous data) 2OR 2-axis data overrun.
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Registers description 8.5 LIS3DH WHO_AM_I (0Fh) Table 24. WHO_AM_I register 0 0 1 1 0 0 1 1 Device identification register. 8.6 CTRL_REG0 (1Eh) Table 25. CTRL_REG0 register SDO_PU_DISC 0 (1) 0(1) 1(2) 0(1) 0(1) 0(1) 0(1) 1. This bit must be set to 0 for correct operation of the device. 2. This bit must be set to 1 for correct operation of the device. Table 26. CTRL_REG0 description Disconnect SDO/SA0 pull-up.
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LIS3DH 8.8 Registers description CTRL_REG1 (20h) Table 29. CTRL_REG1 register ODR3 ODR2 ODR1 ODR0 LPen Zen Yen Xen Table 30. CTRL_REG1 description ODR[3:0] Data rate selection. Default value: 0000 (0000: power-down mode; others: Refer to Table 31: Data rate configuration) Low-power mode enable. Default value: 0 (0: high-resolution mode / normal mode, 1: low-power mode) (Refer to section Section 3.2.1: High-resolution, normal mode, low-power mode) LPen Zen Z-axis enable.
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Registers description 8.9 LIS3DH CTRL_REG2 (21h) Table 32. CTRL_REG2 register HPM1 HPM0 HPCF2 HPCF1 FDS HPCLICK HP_IA2 HP_IA1 Table 33. CTRL_REG2 description HPM[1:0] High-pass filter mode selection. Default value: 00 Refer to Table 34: High-pass filter mode configuration HPCF[2:1] High-pass filter cutoff frequency selection FDS Filtered data selection.
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LIS3DH 8.11 Registers description CTRL_REG4 (23h) Table 37. CTRL_REG4 register BDU BLE(1) FS1 FS0 HR ST1 ST0 SIM 1. The BLE function can be activated only in high-resolution mode. Table 38. CTRL_REG4 description BDU Block data update. Default value: 0 (0: continuous update; 1: output registers not updated until MSB and LSB reading) BLE Big/little endian data selection. Default value 0. (0: Data LSB @ lower address; 1: Data MSB @ lower address) FS[1:0] Full-scale selection.
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Registers description 8.12 LIS3DH CTRL_REG5 (24h) Table 40. CTRL_REG5 register BOOT FIFO_EN -- -- LIR_INT1 D4D_INT1 LIR_INT2 D4D_INT2 Table 41. CTRL_REG5 description 8.13 BOOT Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) FIFO_EN FIFO enable. Default value: 0 (0: FIFO disable; 1: FIFO enable) LIR_INT1 Latch interrupt request on INT1_SRC register, with INT1_SRC (31h) register cleared by reading INT1_SRC (31h) itself. Default value: 0.
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LIS3DH 8.14 Registers description REFERENCE (26h) Table 44. REFERENCE register Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Table 45. REFERENCE register description Ref[7:0] 8.15 Reference value for Interrupt generation. Default value: 0000 0000 STATUS_REG (27h) Table 46. STATUS register ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA Table 47. STATUS register description ZYXOR X, Y and Z-axis data overrun.
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Registers description 8.16 LIS3DH OUT_X_L (28h), OUT_X_H (29h) X-axis acceleration data. The value is expressed as two’s complement left-justified. Please refer to Section 3.2.1: High-resolution, normal mode, low-power mode. 8.17 OUT_Y_L (2Ah), OUT_Y_H (2Bh) Y-axis acceleration data. The value is expressed as two’s complement left-justified. Please refer to Section 3.2.1: High-resolution, normal mode, low-power mode. 8.18 OUT_Z_L (2Ch), OUT_Z_H (2Dh) Z-axis acceleration data.
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LIS3DH 8.20 Registers description FIFO_SRC_REG (2Fh) Table 51. FIFO_SRC_REG register WTM OVRN_FIFO EMPTY FSS4 FSS3 FSS2 FSS1 FSS0 Table 52. FIFO_SRC_REG description 8.21 WTM WTM bit is set high when FIFO content exceeds watermark level OVRN_FIFO OVRN bit is set high when FIFO buffer is full; this means that the FIFO buffer contains 32 unread samples. At the following ODR a new sample set replaces the oldest FIFO value.
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Registers description LIS3DH Write operation at this address is possible only after system boot. Table 55. Interrupt mode AOI 6D Interrupt mode 0 0 OR combination of interrupt events 0 1 6-direction movement recognition 1 0 AND combination of interrupt events 1 1 6-direction position recognition Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’. AOI-6D = ‘01’ is movement recognition. An interrupt is generated when the orientation moves from an unknown zone to known zone.
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LIS3DH 8.23 Registers description INT1_THS (32h) Table 58. INT1_THS register 0 THS6 THS5 THS4 THS3 THS2 THS1 THS0 D1 D0 Table 59. INT1_THS description THS[6:0] 8.24 Interrupt 1 threshold. Default value: 000 0000 1 LSb = 16 mg @ FS = ±2 g 1 LSb = 32 mg @ FS = ±4 g 1 LSb = 62 mg @ FS = ±8 g 1 LSb = 186 mg @ FS = ±16 g INT1_DURATION (33h) Table 60. INT1_DURATION register 0 D6 D5 D4 D3 D2 Table 61. INT1_DURATION description D[6:0] Duration value.
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Registers description 8.25 LIS3DH INT2_CFG (34h) Table 62. INT2_CFG register AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE Table 63. INT2_CFG description AOI AND/OR combination of interrupt events. Default value: 0 (see Table 64) 6D 6-direction detection function enabled. Default value: 0. Refer to Table 64. ZHIE Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel.
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LIS3DH 8.26 Registers description INT2_SRC (35h) Table 65. INT2_SRC register 0 IA ZH ZL YH YL XH XL Table 66. INT2_SRC description IA Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) ZH Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred) ZL Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred) YH Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred) YL Y low.
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Registers description 8.28 LIS3DH INT2_DURATION (37h) Table 69. INT2_DURATION register 0 D6 D5 D4 D3 D2 D1 D0 Table 70. INT2_DURATION description Duration value. Default value: 000 0000 1 LSb = 1/ODR(1) D[6:0] 1. Duration time is measured in N/ODR, where N is the content of the duration register. The D[6:0] bits set the minimum duration of the Interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen. 8.29 CLICK_CFG (38h) Table 71.
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LIS3DH 8.30 Registers description CLICK_SRC (39h) Table 73. CLICK_SRC register IA DCLICK SCLICK Sign Z Y X Table 74. CLICK_SRC description 8.31 IA Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) DCLICK Double-click enable. Default value: 0 (0:double-click detection disabled, 1: double-click detection enabled) SCLICK Single-click enable.
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Registers description 8.33 LIS3DH TIME_LATENCY (3Ch) Table 79. TIME_LATENCY register TLA7 TLA6 TLA5 TLA4 TLA3 TLA2 TLA1 TLA0 TW1 TW0 Acth1 Acth0 Table 80. TIME_LATENCY description TLA[7:0] 8.34 Click time latency. Default value: 0000 0000 TIME WINDOW (3Dh) Table 81. TIME_WINDOW register TW7 TW6 TW5 TW4 TW3 TW2 Table 82. TIME_WINDOW description TW[7:0] 8.35 Click time window ACT_THS (3Eh) Table 83. ACT_THS register -- Acth6 Acth5 Acth4 Acth3 Acth2 Table 84.
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LIS3DH 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
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Package information 9.1 LIS3DH LGA-16 package information Figure 12.
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LIS3DH 9.2 Package information LGA-16 packing information Figure 13. Carrier tape information for LGA-16 package Figure 14.
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Package information LIS3DH Figure 15. Reel information for carrier tape of LGA-16 package 7 PP PLQ $FFHVV KROH DW VORW ORFDWLRQ % & $ 1 ' )XOO UDGLXV * PHDVXUHG DW KXE 7DSH VORW LQ FRUH IRU WDSH VWDUW PP PLQ ZLGWK Table 87. Reel dimensions for carrier tape of LGA-16 package Reel dimensions (mm) 52/54 A (max) 330 B (min) 1.5 C 13 ±0.25 D (min) 20.2 N (min) 60 G 12.4 +2/-0 T (max) 18.
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LIS3DH 10 Revision history Revision history Table 88. Document revision history Date Revision 21-May-2010 1 Initial release 2 Updated Table 1: Device summary Updated Features and Figure 1: Block diagram Updated Table 2: Pin description and Table 14: Serial interface pin description Added Table 3: Internal pull-up values (typ.) for SDO/SA0 pin Updated Table 9: Absolute maximum ratings Updated Section 3.
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LIS3DH IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.