Datasheet

ManualsBrandsST ManualsIntegrated Circuits (ICs)Acceleration Sensor LGA-16 (4x7)

January 2008 Rev 2 1/48

LIS3LV02DL

MEMS inertial sensor

3-axis - ±2g/±6g digital output low voltage linear accelerometer

Features

■ 2.16 V to 3.6 V single supply operation

■ 1.8 V compatible IOs

■ I

C/SPI digital output interfaces

■ Programmable 12 or 16 bit data representation

■ Interrupt activated by motion

■ Programmable interrupt threshold

■ Embedded self test

■ High shock survivability

■ ECOPACK® compliant (see Section 9)

Description

The LIS3LV02DL is a three axes digital output

linear accelerometer that includes a sensing

element and an IC interface able to take the

information from the sensing element and to

provide the measured acceleration signals to the

external world through an I

C/SPI serial interface.

The sensing element, capable of detecting the

acceleration, is manufactured using a dedicated

process developed by ST to produce inertial

sensors and actuators in silicon.

The IC interface instead is manufactured using a

CMOS process that allows high level of

integration to design a dedicated circuit which is

factory trimmed to better match the sensing

element characteristics.

The LIS3LV02DL has a user selectable full scale

of ±2g, ±6g and it is capable of measuring

acceleration over a bandwidth of 640 Hz for all

axes. The device bandwidth may be selected

accordingly to the application requirements.

The self-test capability allows the user to check

the functioning of the device.

The device may be also configured to generate an

inertial wake-up/free-fall interrupt signal when a

programmable acceleration threshold is crossed

at least in one of the three axes.

The LIS3LV02DL is available in plastic SMD

package and it is specified over a temperature

range extending from -40°C to +85°C.

The LIS3LV02DL belongs to a family of products

suitable for a variety of applications:

– Free-Fall detection

– Motion activated functions in portable

terminals

– Antitheft systems and Inertial navigation

– Gaming and virtual reality input devices

– Vibration monitoring and compensation

LGA-16

Table 1. Device summary

Order code

Operating temperature

range [° C]

Package Packing

LIS3LV02DL -40 to +85 LGA-16 Tray

LIS3LV02DLTR -40 to +85 LGA-16 Tape and reel

www.st.com

Summary of content (48 pages)

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LIS3LV02DL MEMS inertial sensor 3-axis - ±2g/±6g digital output low voltage linear accelerometer Features ■ 2.16 V to 3.6 V single supply operation ■ 1.
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Content LIS3LV02DL Content 1 2 3 4 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 LGA-16 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Mechanical characteristics . . . . . . . . . . . . . .
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LIS3LV02DL 7 Content Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 OFFSET_X (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 OFFSET_Y (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 OFFSET_Z (18h) . . . . . . . . . . . . . . . . .
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Content 8 LIS3LV02DL Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 Mechanical characteristics at 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2 Mechanical characteristics derived from measurement in the -40°C to +85°C temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3 Electro-mechanical characteristics at 25°C . . . . . . . . . . . . . . . . . . . . . . .
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LIS3LV02DL List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection . . . . . . . . . . . . .
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List of tables LIS3LV02DL List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47.
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LIS3LV02DL Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. List of tables Register description (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Register (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Block diagram and pin description LIS3LV02DL 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram X+ Y+ Z+ a Filter CS DE MUX MUX Reconstruction Σ∆ CHARGE AMPLIFIER Reconstruction Σ∆ Regs Array Filter Z- I2C SCL/SPC SDA/SDO/SDI SPI SDO Y- SELF TEST Filter TRIMMING CIRCUITS REFERENCE CONTROL LOGIC & INTERRUPT GEN. CLOCK CS Y VDD_IO 1 6 NC X (TOP VIEW) CK 8 DIRECTION OF THE DETECTABLE ACCELERATIONS Table 2.
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LIS3LV02DL Block diagram and pin description Table 2.
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Mechanical and electrical specifications LIS3LV02DL 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Table 3. Mechanical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted(1) Symbol FS Dres Parameter Measurement range(3) Min. Typ.(2) FS bit set to 0 ±1.7 ±2.0 FS bit set to 1 ±5.3 ±6.0 Test conditions Full-scale = ±2 g ODR1=40 Hz 1.0 Full-scale = ±2 g ODR2=160 Hz 2.0 Device resolution mg Full-scale = ±2 g ODR3=640 Hz 3.
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LIS3LV02DL Table 3. Symbol Mechanical and electrical specifications Mechanical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted(1) (continued) Parameter Test conditions Min. Best fit straight line X, Y axis Full-scale = ±2 g ODR=40 Hz NL Vst Max. Non Linearity %FS Cross axis Self test output Unit ±2 Best fit straight line Z axis Full-scale = ±2 g ODR=40 Hz CrAx Typ.(2) ±3 -3.5 change(7),(8) BW System Bandwidth(9) Top Operating Temperature Range Wh Product Weight 3.
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Mechanical and electrical specifications Table 4. Symbol FS Dres LIS3LV02DL Mechanical characteristics @ Vdd=2.5 V, T=25 °C unless otherwise noted(1) Parameter Measurement range(3) Min. Typ.(2) FS bit set to 0 ±1.7 ±2.0 FS bit set to 1 ±5.3 ±6.0 Test conditions Full-scale = ±2g ODR1=40Hz 1.0 Full-scale = ±2g ODR2=160Hz 2.0 Device resolution mg Full-scale = ±2g ODR3=640Hz 3.9 Full-scale = ±2g ODR4=2560Hz 15.
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LIS3LV02DL Table 4. Symbol Mechanical and electrical specifications Mechanical characteristics @ Vdd=2.5 V, T=25 °C unless otherwise noted(1) (continued) Parameter Test conditions Min. Best fit straight line X, Y axis Full-scale = ±2g ODR=40Hz NL Vst Max. Non linearity %FS Cross axis Self test output Unit ±2 Best fit straight line Z axis Full-scale = ±2g ODR=40Hz CrAx Typ.(2) ±3 -3.5 change(7),(8) BW System bandwidth(9) Top Operating temperature range Wh Product weight 3.
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Mechanical and electrical specifications LIS3LV02DL 2.2 Electrical characteristics Table 5. Electrical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted (1) Symbol Vdd Vdd_IO Idd Min. Typ.(2) Max. Unit Supply voltage 2.16 3.3 3.6 V I/O pads supply voltage 1.71 Vdd V Parameter Test conditions Vdd = 3.3 V 0.65 0.80 Vdd = 2.5 V 0.60 0.
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LIS3LV02DL Mechanical and electrical specifications 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 6.
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Mechanical and electrical specifications 2.3.2 LIS3LV02DL I2C - Inter IC control interface Subject to general operating conditions for Vdd and Top. Table 7. I2C slave timing values I2C standard mode (1) Symbol I2C fast mode (1) Parameter f(SCL) Unit SCL clock frequency Min Max Min Max 0 100 0 400 tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0(2) KHz µs ns 3.45 0(2) 0.
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LIS3LV02DL 2.4 Mechanical and electrical specifications Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 8.
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Mechanical and electrical specifications 2.5 Terminology 2.5.1 Sensitivity LIS3LV02DL Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so, ±1g acceleration is applied to the sensor.
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LIS3LV02DL 3 Functionality Functionality The LIS3LV02DL is a high performance, low-power, digital output 3-axis linear accelerometer packaged in an LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I2C/SPI serial interface. 3.1 Sensing element A proprietary process is used to create a surface micro-machined accelerometer.
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Functionality 3.3 LIS3LV02DL Factory calibration The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off). The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation. This allows the user to employ the device without further calibration.
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LIS3LV02DL 4 Application hints Application hints Figure 5. LIS3LV02DL electrical connection Vdd_IO 1 Y RDY/INT SDO SDA/SDI/SDO SCL/SPC CS Z 1 6 X LIS3LV02DL 7 16 (TOP VIEW) 8 9 DIRECTION OF THE DETECTABLE ACCELERATIONS 15 14 Vdd 100nF 10uF GND Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line.
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Digital interfaces 5 LIS3LV02DL Digital interfaces The registers embedded inside the LIS3LV02DL may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS line must be tied high (i.e connected to Vdd_IO). Table 9.
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LIS3LV02DL 5.1.1 Digital interfaces I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy.
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Digital interfaces LIS3LV02DL Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. DATA is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state.
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LIS3LV02DL Digital interfaces bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode).
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Digital interfaces LIS3LV02DL Figure 8. Multiple bytes SPI read protocol (2 bytes example) CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8 5.2.2 SPI write Figure 9. SPI write protocol CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit.
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LIS3LV02DL 5.2.3 Digital interfaces SPI Read in 3-wires mode 3-wires mode is entered by setting to ‘1’ bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2. Figure 11. SPI read protocol in 3-wires mode CS SPC SDI/O DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0).
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Register mapping 6 LIS3LV02DL Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses. Table 15.
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LIS3LV02DL Table 15.
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Register description 7 LIS3LV02DL Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers 7.2 to 7.7 contain the factory calibration values, it is not necessary to change their value for normal device operation. 7.1 WHO_AM_I (0Fh) Table 16. W7 Table 17.
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LIS3LV02DL Register description Table 23. OZ7, OZ0 7.5 GX7 Table 25. GX7, GX0 GY7 Table 27. GY7, GY0 GX6 GX5 GX4 GX3 GX2 GX1 GX0 GY3 GY2 GY1 GY0 GZ3 GZ2 GZ1 GZ0 ST Zen Yen Xen Register description (19h) Digital Gain Trimming for X-Axis Register (1Ah) GY6 GY5 GY4 Register description (1Ah) Digital Gain Trimming for Y-Axis GAIN_Z (1Bh) Table 28. GZ7 Table 29. GZ7, GZ0 7.8 Register (19h) GAIN_Y (1Ah) Table 26. 7.7 Digital Offset Trimming for Z-Axis GAIN_X (19h) Table 24.
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Register description Table 31. LIS3LV02DL Register description (continued) (20h) ST Self Test Enable (0: normal mode; 1: self-test active) Zen Z-axis enable (0: axis off; 1: axis on) Yen Y-axis enable (0: axis off; 1: axis on) Xen X-axis enable (0: axis off; 1: axis on) PD1, PD0 bit allows to turn the device out of power-down mode. The device is in powerdown mode when PD1, PD0= “00” (default value after boot). The device is in normal mode when either PD1 or PD0 is set to 1.
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LIS3LV02DL Register description Table 33. Register description (continued) (21h) SIM SPI Serial Interface Mode selection (0: 4-wire interface; 1: 3-wire interface) DAS Data Alignment Selection (0: 12 bit right justified; 1: 16 bit left justified) FS bit is used to select Full Scale value. After the device power-up the default full scale value is +/-2g. In order to obtain a +/-6g full scale it is necessary to set FS bit to ‘1’.
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Register description 7.10 LIS3LV02DL CTRL_REG3 (22h) Table 34. ECK Table 35. Register (22h) HPDD HPFF FDS res res CFS1 CFS0 Register description (22h) ECK External Clock. Default value: 0 (0: clock from internal oscillator; 1: clock from external pad) HPDD High Pass filter enabled for Direction Detection. Default value: 0 (0: filter bypassed; 1: filter enabled) HPFF High Pass filter enabled for Free-Fall and Wake-Up.
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LIS3LV02DL Register description Table 37. Register description (continued) (27h) ZYXDA X, Y and Z axis new Data Available ZDA Z axis new Data Available YDA Y axis new Data Available XDA X axis new Data Available The content of this register is updated every ODR cycle, regardless of BDU bit value in CTRL_REG2. 7.13 OUTX_L (28h) Table 38. XD7 Table 39.
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Register description Table 43. YD7, YD0 LIS3LV02DL Register description (2Ah) Y axis acceleration data LSB In Big Endian Mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the MSB acceleration data and depends on bit DAS in CTRL_REG2 register as described in the following section. 7.16 OUTY_H (2Bh) Table 44. YD15 Table 45.
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LIS3LV02DL Register description In Big Endian Mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the LSB acceleration data. 7.19 FF_WU_CFG (30h) Table 50. AOI Table 51. Register (30h) LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Register description (30h) AOI And/Or combination of Interrupt events. Default value: 0. (0: OR combination of interrupt events; 1: AND combination of interrupt events) LIR Latch interrupt request. Default value: 0.
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Register description Table 53. 7.21 LIS3LV02DL Register description (31h) IA Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) ZH Z High. Default value: 0 (0: no interrupt; 1: Z High event has occurred) ZL Z Low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) YH Y High. Default value: 0 (0: no interrupt; 1: Y High event has occurred) YL Y Low.
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LIS3LV02DL 7.24 Register description FF_WU_DURATION (36h) Table 58. Register (36h) FWD7 Table 59. FWD6 FWD5 FWD4 FWD3 FWD2 FWD1 FWD0 Register description (36h) FWD7, FWD0 Minimum duration of the Free-fall/Wake-up event This register sets the minimum duration of the free-fall/wake-up event to be recognized. FF_WU_DURATION (Dec) Duration ( s ) = -----------------------------------------------------------------------ODR 7.25 DD_CFG (38h) Table 60. IEND Table 61.
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Register description Table 61. LIS3LV02DL Register description (continued) (38h) XHIE Enable interrupt generation on X High event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) XLIE Enable interrupt generation on X Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Direction-detector configuration register. 7.
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LIS3LV02DL 7.27 Register description DD_ACK (3Ah) Dummy register. If LIR bit in DD_CFG register is set to ‘1’, a reading at this address allows the DD_SRC register refresh. Read data is not significant. 7.28 DD_THSI_L (3Ch) Table 64. Register (3Ch) THSI7 Table 65. THSI6 THSI15 Table 67.
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Typical performance characteristics LIS3LV02DL 8 Typical performance characteristics 8.1 Mechanical characteristics at 25°C Figure 12. X-axis zero-g level at 3.3 V Figure 13. X-axis sensitivity at 3.3 V 20 25 18 16 20 Percent of parts [%] Percent of parts [%] 14 12 10 8 15 10 6 4 5 2 0 −60 −40 −20 0 20 Zero−g Level Offset [mg] 40 25 25 20 20 15 10 5 0 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 1100 1120 Figure 15. Y-axis sensitivity at 3.
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LIS3LV02DL Typical performance characteristics Figure 16. Z-axis zero-g level at 3.3 V Figure 17. Z-axis Sensitivity at 3.3 V 25 30 25 Percent of parts [%] Percent of parts [%] 20 15 10 20 15 10 5 5 0 8.2 −60 −40 −20 0 20 Zero−g Level Offset [mg] 40 0 60 940 960 980 1000 1020 1040 Sensitivity [LSB/g] 1060 1080 1100 1120 Mechanical characteristics derived from measurement in the -40°C to +85°C temperature range Figure 18. X-axis zero-g level change vs. temperature at 3.
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Typical performance characteristics LIS3LV02DL Figure 20. Y-axis zero-g level change vs. temperature at 3.3 V Figure 21. Y-axis sensitivity change vs. temperature at 3.3 V 40 25 35 20 Percent of parts [%] Percent of parts [%] 30 25 20 15 15 10 10 5 5 0 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 o Zero−g Level drift [mg/ C] 0.6 0.8 0 −0.015 1 Figure 22. Z-axis zero-g level change vs. temperature at 3.3 V −0.01 −0.005 0 0.005 o Sensitivity drift [%/ C] 0.01 0.015 0.02 Figure 23.
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LIS3LV02DL Typical performance characteristics Figure 26. Current consumption in PowerDown mode (Vdd=3.3 V) Figure 27. Current consumption in operational mode (Vdd=3.3 V) 35 16 14 30 12 Percent of parts [%] Percent of parts [%] 25 20 15 10 8 6 10 4 5 0 −5 2 −2.5 0 Current consumption [uA] 2.
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Package information 9 LIS3LV02DL Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK® is an ST trademark. ECOPACK® specifications are available at: www.
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LIS3LV02DL 10 Revision history Revision history Table 72. Document revision history Date Revision 15-Feb-2006 1 Initial release. 2 Added two new sections: Section 2.3: Communication interface characteristics and Section 8: Typical performance characteristics.
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LIS3LV02DL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.