Datasheet

Digital interfaces LIS3LV02DL
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5 Digital interfaces
The registers embedded inside the LIS3LV02DL may be accessed through both the I
2
C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I
2
C interface, CS
line must be tied high (i.e connected to Vdd_IO).
5.1 I
2
C serial interface
The LIS3LV02DL I
2
C is a bus slave. The I
2
C is employed to write the data into the registers
whose content can also be read back.
The relevant I
2
C terminology is given in the table below.
There are two signals associated with the I
2
C bus: the Serial Clock Line (SCL) and the
Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the
data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor
embedded inside the LIS3LV02DL. When the bus is free both the lines are high.
The I
2
C interface is compliant with Fast Mode (400 kHz) I
2
C standards as well as the
Normal Mode.
Table 9. Serial interface pin description
Pin name Pin description
CS
SPI enable
I
2
C/SPI mode selection (1: I
2
C mode; 0: SPI enabled)
SCL/SPC
I
2
C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
SDA/SDI/SDO
I
2
C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SDO SPI Serial Data Output (SDO)
Table 10. Serial interface pin description
Term Description
Transmitter The device which sends data to the bus
Receiver The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave The device addressed by the master