Datasheet

Register description LIS3LV02DL
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PD1, PD0 bit allows to turn the device out of power-down mode. The device is in power-
down mode when PD1, PD0= “00” (default value after boot). The device is in normal mode
when either PD1 or PD0 is set to 1.
DF1, DF0 bit allows to select the data rate at which acceleration samples are produced. The
default value is “00” which corresponds to a data-rate of 40 Hz. By changing the content of
DF1, DF0 to “01”, “10” and “11” the selected data-rate will be set respectively equal to
160 Hz, 640 Hz and to 2560 Hz.
ST bit is used to activate the self test function. When the bit is set to one, an output change
will occur to the device outputs (refer to table 2 and 3 for specification) thus allowing to
check the functionality of the whole measurement chain.
Zen bit enables the Z-axis measurement channel when set to 1. The default value is 1.
Yen bit enables the Y-axis measurement channel when set to 1. The default value is 1.
Xen bit enables the X-axis measurement channel when set to 1. The default value is 1.
7.9 CTRL_REG2 (21h)
ST
Self Test Enable
(0: normal mode; 1: self-test active)
Zen
Z-axis enable
(0: axis off; 1: axis on)
Ye n
Y-axis enable
(0: axis off; 1: axis on)
Xen
X-axis enable
(0: axis off; 1: axis on)
Table 31. Register description (continued) (20h)
Table 32. Register (21h)
FS BDU BLE BOOT IEN DRDY SIM DAS
Table 33. Register description (21h)
FS
Full Scale selection
(0: ±2g; 1: ±6g)
BDU
Block Data Update
(0: continuous update; 1: output registers not updated between MSB and LSB
reading)
BLE
Big/Little Endian selection
(0: little endian; 1: big endian)
BOOT Reboot memory content
IEN
Interrupt ENable
(0: data ready on RDY pad; 1: interrupt events on RDY pad)
DRDY Enable Data-Ready generation