Datasheet

LIS3LV02DL Register description
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The content of this register is updated every ODR cycle, regardless of BDU bit value in
CTRL_REG2.
7.13 OUTX_L (28h)
In Big Endian Mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the
MSB acceleration data and depends on bit DAS in CTRL_REG2 register as described in the
following section.
7.14 OUTX_H (29h)
When reading the register in “12 bit right justified” mode the most significant bits (15:12) are
replaced with bit 11 (i.e. XD15-XD12=XD11, XD11, XD11, XD11).
In Big Endian Mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the LSB
acceleration data.
7.15 OUTY_L (2Ah)
ZYXDA X, Y and Z axis new Data Available
ZDA Z axis new Data Available
YDA Y axis new Data Available
XDA X axis new Data Available
Table 37. Register description (continued) (27h)
Table 38. Register (28h)
XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0
Table 39. Register description (28h)
XD7, XD0 X axis acceleration data LSB
Table 40. Register (29h)
XD15 XD14 XD13 XD12 XD11 XD10 XD9 XD8
Table 41. Register description (29h)
XD15, XD8 X axis acceleration data MSB
Table 42. Register (2Ah)
YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0