Datasheet

Register description LIS3LV02DL
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7.21 FF_WU_ACK (32h)
Dummy register. If LIR bit in FF_WU_CFG register is set to ‘1’, a reading at this address
allows the FF_WU_SRC register refresh. Read data is not significant.
7.22 FF_WU_THS_L (34h)
7.23 FF_WU_THS_H (35h)
Table 53. Register description (31h)
IA
Interrupt Active. Default value: 0
(0: no interrupt has been generated;
1: one or more interrupt events have been generated)
ZH
Z High. Default value: 0
(0: no interrupt; 1: Z High event has occurred)
ZL
Z Low. Default value: 0
(0: no interrupt; 1: Z Low event has occurred)
YH
Y High. Default value: 0
(0: no interrupt; 1: Y High event has occurred)
YL
Y Low. Default value: 0
(0: no interrupt; 1: Y Low event has occurred)
XH
X High. Default value: 0
(0: no interrupt; 1: X High event has occurred)
XL
X Low. Default value: 0
(0: no interrupt; 1: X Low event has occurred)
Table 54. Register (34h)
THS7 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 55. Register description (34h)
THS7, THS0 Free-fall / Inertial Wake Up Acceleration Threshold LSB
Table 56. Register (35h)
THS15 THS14 THS13 THS12 THS11 THS10 THS9 THS8
Table 57. Register description (35h)
THS15, THS8 Free-fall / Inertial Wake Up Acceleration Threshold MSB