Datasheet

LIS3LV02DL Register description

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7.27 DD_ACK (3Ah)

Dummy register. If LIR bit in DD_CFG register is set to ‘1’, a reading at this address allows

the DD_SRC register refresh. Read data is not significant.

7.28 DD_THSI_L (3Ch)

7.29 DD_THSI_H (3Dh)

7.30 DD_THSE_L (3Eh)

7.31 DD_THSE_H (3Fh)

Table 64. Register (3Ch)

THSI7 THSI6 THSI5 THSI4 THSI3 THSI2 THSI1 THSI0

Table 65. Register description (3Ch)

THSI7, THSI0 Direction detection Internal Threshold LSB

Table 66. Register (3Dh)

THSI15 THSI14 THSI13 THSI12 THSI11 THSI10 THSI9 THSI8

Table 67. Register description (3Dh)

THSI15, THSI8 Direction detection Internal Threshold MSB

Table 68. Register (3Eh)

THSE7 THSE6 THSE5 THSE4 THSE3 THSE2 THSE1 THSE0

Table 69. Register description (3Eh)

THSE7, THSE0 Direction detection External Threshold LSB

Table 70. Register (3Fh)

THSE15 THSE14 THSE13 THSE12 THSE11 THSE10 THSE9 THSE8

Table 71. Register description (3Fh)

THSE15, THSE8 Direction detection External Threshold MSB