Datasheet

Block diagram and pin description LIS3LV02DL
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1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 LGA-16 pin description
Figure 2. Pin connection
Σ∆
CHARGE
AMPLIFIER
MUX
Y+
Z+
Y-
Z-
Regs
a
X+
X-
DE
MUX
Reconstruction
Filter
Σ∆
Σ∆
Array
I
2
C
SPI
CS
SCL/SPC
SDA/SDO/SDI
SDO
CONTROL LOGIC
&
INTERRUPT GEN.
RDY/INT
Reconstruction
Filter
Reconstruction
Filter
CLOCK
TRIMMING
CIRCUITS
REFERENCESELF TEST
Table 2. Pin description
Pin# Name Function
1 RDY/INT Data ready/inertial wake-up interrupt
2 SDO SPI Serial Data Output
Y
1
X
Z
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
LIS3LV02DL
(TOP VIEW)
1
6
7
8
9
14
15
16
CS
SCL/SPC
VDD_IO
SDO RDY/INT
GND
RES
VDD
RES
VDD
GND
NC
CK
GND
RES
SDA/SDI/SDO