Datasheet

ManualsBrandsST ManualsIntegrated Circuits (ICs)iNEMO Inertial Module, 3D Digital Accelerometer, Digital, 16bit, LGA

This is information on a product in full production.

September 2017 DocID028475 Rev 7 1/114

LSM6DSL

iNEMO inertial module:

always-on 3D accelerometer and 3D gyroscope

Datasheet - production data

Features

 Power consumption: 0.4 mA in combo normal mode

and 0.65 mA in combo high-performance mode

 “Always-on” experience with low power

consumption for both accelerometer and gyroscope

 Smart FIFO up to 4 kbyte based on features set

 Android M compliant

 Hard, soft ironing for external magnetic sensor

corrections

 ±2/±4/±8/±16 g full scale

 ±125/±250/±500/±1000/±2000 dps full scale

 Analog supply voltage: 1.71 V to 3.6 V

 Independent IOs supply (1.62 V)

 Compact footprint, 2.5 mm x 3 mm x 0.83 mm

 SPI & I

C serial interface with main processor data

synchronization feature

 Pedometer, step detector and step counter

 Significant motion and tilt function

 Standard interrupts: free-fall, wakeup, 6D/4D

orientation, click and double-click

 Embedded temperature sensor

 ECOPACK

, RoHS and “Green” compliant

Applications

 Motion tracking and gesture detection

 Collecting sensor data

 Indoor navigation

 IoT and connected devices

 Intelligent power saving for handheld devices

 Vibration monitoring and compensation

Description

The LSM6DSL is a system-in-package featuring a 3D

digital accelerometer and a 3D digital gyroscope

performing at 0.65 mA in high-performance mode and

enabling always-on low-power features for an optimal

motion experience for the consumer.

The LSM6DSL supports main OS requirements,

offering real, virtual and batch sensors with 4 kbyte for

dynamic data batching.

ST’s family of MEMS sensor modules leverages the

robust and mature manufacturing processes already

used for the production of micromachined

accelerometers and gyroscopes.

The various sensing elements are manufactured using

specialized micromachining processes, while the IC

interfaces are developed using CMOS technology that

allows the design of a dedicated circuit which is

trimmed to better match the characteristics of the

sensing element.

The LSM6DSL has a full-scale acceleration range of

±2/±4/±8/±16 g and an angular rate range of

±125/±250/±500/±1000/±2000 dps.

High robustness to mechanical shock makes the

LSM6DSL the preferred choice of system designers for

the creation and manufacturing of reliable products.

The LSM6DSL is available in a plastic land grid array

(LGA) package.

LGA-14L

(2.5 x 3 x 0.83 mm) typ.

Table 1. Device summary

Part number

Temp.

range [°C]

Package Packing

LSM6DSL -40 to +85

LGA-14L

(2.5x3x0.83mm)

Tray

LSM6DSLTR -40 to +85

Tape &

Reel

www.st.com

Summary of content (114 pages)

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LSM6DSL iNEMO inertial module: always-on 3D accelerometer and 3D gyroscope Datasheet - production data Description The LSM6DSL is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope performing at 0.65 mA in high-performance mode and enabling always-on low-power features for an optimal motion experience for the consumer. LGA-14L (2.5 x 3 x 0.83 mm) typ.
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Contents LSM6DSL Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 Embedded low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 2.1 Tilt detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Absolute wrist tilt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin description . . . . . . . . . .
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LSM6DSL 6 Contents 5.5.5 Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5.6 FIFO reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 I2C/SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2 Master I2C . . . . . . . . . . . . . . . . . . . . . .
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Contents 4/114 LSM6DSL 9.16 CTRL4_C (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.17 CTRL5_C (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.18 CTRL6_C (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.19 CTRL7_G (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.20 CTRL8_XL (17h) . . . . . . . . .
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LSM6DSL Contents 9.49 SENSORHUB9_REG (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.50 SENSORHUB10_REG (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.51 SENSORHUB11_REG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.52 SENSORHUB12_REG (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.53 FIFO_STATUS1 (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents LSM6DSL 9.82 MD2_CFG (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.83 MASTER_CMD_CODE (60h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.84 SENS_SYNC_SPI_ERROR_CODE (61h) . . . . . . . . . . . . . . . . . . . . . . . . 93 9.85 OUT_MAG_RAW_X_L (66h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.86 OUT_MAG_RAW_X_H (67h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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LSM6DSL Contents 11.19 MAG_SI_XY (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.20 MAG_SI_XZ (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.21 MAG_SI_YX (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.22 MAG_SI_YY (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.23 MAG_SI_YZ (29h) . . . . . . . . . . . . . . . . . . . .
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List of tables LSM6DSL List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48.
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LSM6DSL List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96.
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List of tables Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145.
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LSM6DSL List of tables Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Table 171. Table 172. Table 173. Table 174. Table 175. Table 176. Table 177. Table 178. Table 179. Table 180. Table 181. Table 182. Table 183. Table 184. Table 185. Table 186. Table 187. Table 188. Table 189. Table 190. Table 191. Table 192. Table 193. Table 194. Table 195. Table 196.
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List of tables Table 205. Table 206. Table 207. Table 208. Table 209. Table 210. Table 211. Table 212. Table 213. Table 214. Table 215. Table 216. Table 217. Table 218. Table 219. Table 220. Table 221. Table 222. Table 223. Table 224. Table 225. Table 226. Table 227. Table 228. Table 229. Table 230. Table 231. Table 232. Table 233. Table 234. Table 235. Table 236. Table 237. Table 238. Table 239. Table 240. Table 241. Table 242. Table 243. Table 244. Table 245. Table 246. Table 247. Table 248. Table 249.
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LSM6DSL List of tables Table 257. Table 258. Table 259. Table 260. Table 261. Table 262. Table 263. Table 264. Table 265. Table 266. Table 267. Table 268. Table 269. Table 270. Table 271. Table 272. Table 273. Table 274. Table 275. Table 276. Table 277. Table 278. Table 279. Table 280. Table 281. Table 282. Table 283. Table 284. Table 285. Table 286. Table 287. Table 288. Table 289. Table 290. Table 291. Table 292. Table 293. Table 294. Table 295. Table 296. STEP_COUNT_DELTA register . . . . . . . . . .
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List of figures LSM6DSL List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. 14/114 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 LSM6DSL connection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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LSM6DSL 1 Overview Overview The LSM6DSL is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope. The integrated power-efficient modes are able to reduce the power consumption down to 0.65 mA in high-performance mode, combining always-on low-power features with superior sensing precision for an optimal motion experience for the consumer thanks to ultra-low noise performance for both the gyroscope and accelerometer.
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Embedded low-power features 2 LSM6DSL Embedded low-power features The LSM6DSL has been designed to be fully compliant with Android, featuring the following on-chip functions:  4 kbyte data buffering – 100% efficiency with flexible configurations and partitioning – Possibility to store timestamp  Event-detection interrupts (fully configurable): – Free-fall – Wakeup – 6D orientation – Click and double-click sensing – Activity / inactivity recognition  Specific IP blocks with negligible power consumption
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LSM6DSL 2.2 Embedded low-power features Absolute wrist tilt The LSM6DSL implements in hardware the Absolute Wrist Tilt (AWT) function which allows detecting when the angle between a selectable accelerometer semi-axis and the horizontal plane becomes higher than a specific user-selectable value.
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Pin description 3 LSM6DSL Pin description Figure 1. Pin connections Z Y X (1) NC (1) NC ΩY ΩR ΩP 1. Leave pin electrically unconnected and soldered to PCB.
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LSM6DSL 3.1 Pin description Pin connections The LSM6DSL offers flexibility to connect the pins in order to have two different mode connections and functionalities. In detail:  Mode 1: I2C slave interface or SPI (3- and 4-wire) serial interface is available;  Mode 2: I2C slave interface or SPI (3- and 4-wire) serial interface and I2C interface master for external sensor connections are available; Figure 2.
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Pin description LSM6DSL Table 2.
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LSM6DSL Module specifications 4 Module specifications 4.1 Mechanical characteristics @ Vdd = 1.8 V, T = 25 °C unless otherwise noted. Table 3. Mechanical characteristics Symbol Parameter Test conditions Min. Typ.(1) Max. Unit ±2 LA_FS ±4 Linear acceleration measurement range ±8 g ±16 ±125 G_FS ±250 Angular rate measurement range ±500 dps ±1000 ±2000 LA_So G_So G_So% Linear acceleration sensitivity(2) Angular rate sensitivity Sensitivity tolerance (2) (3) FS = ±2 0.
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Module specifications LSM6DSL Table 3. Mechanical characteristics (continued) Symbol RnRMS An RMS LA_ODR G_ODR Vst Top Parameter Test conditions Min. Gyroscope RMS noise in normal/low-power mode(7) Acceleration noise density in high-performance mode(8) Acceleration RMS noise in normal/low-power mode(9)(10) Typ.(1) 75 FS = ±2 g 80 FS = ±4 g 80 FS = ±8 g 90 FS = ±16 g 130 FS = ±2 g 1.8 FS = ±4 g 2.0 FS = ±8 g 2.4 FS = ±16 g 3.0 Linear acceleration output data rate 1.6(11) 12.
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LSM6DSL Module specifications 6. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting. 7. Gyroscope RMS noise in normal/low-power mode is independent of the ODR and FS setting. 8. Accelerometer noise density in high-performance mode is independent of the ODR. 9. Accelerometer RMS noise in normal/low-power mode is independent of the ODR. 10. Noise RMS related to BW = ODR /2 (for ODR /9, typ value can be calculated by Typ *0.6). 11.
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Module specifications 4.2 LSM6DSL Electrical characteristics @ Vdd = 1.8 V, T = 25 °C unless otherwise noted. Table 4. Electrical characteristics Symbol Vdd Vdd_IO Min. Typ.(1) Max. Unit Supply voltage 1.71 1.8 3.6 V Power supply for I/O 1.62 3.6 V Parameter Test conditions IddHP Gyroscope and accelerometer current consumption in high-performance mode ODR = 1.6 kHz 0.65 mA IddNM Gyroscope and accelerometer current consumption in normal mode ODR = 208 Hz 0.
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LSM6DSL 4.3 Module specifications Temperature sensor characteristics @ Vdd = 1.8 V, T = 25 °C unless otherwise noted. Table 5. Temperature sensor characteristics Symbol TODR(2) Toff Parameter Test condition Min. Temperature refresh rate Temperature offset (3) TSen Temperature sensitivity TST Temperature stabilization time(4) Operating temperature range Max. 52 -15 +15 °C LSB/°C 500 16 -40 Unit Hz 256 T_ADC_res Temperature ADC resolution Top Typ.(1) μs bit +85 °C 1.
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Module specifications LSM6DSL 4.4 Communication interface characteristics 4.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 6.
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LSM6DSL 4.4.2 Module specifications I2C - inter-IC control interface Subject to general operating conditions for Vdd and Top. Figure 4. I2C timing diagram 5(3($7(' 67$57 67$57 WVX 65 WZ 63 65 6'$ 67$57 WK 6'$ WVX 6'$ 6723 WVX 63 6&/ WK 67 Note: WZ 6&// WZ 6&/+ Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. 4.4.2.1 I2C slave Table 7.
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Module specifications LSM6DSL 4.4.2.2 I2C master When in I2C Master Mode, an external sensor can be connected to LSM6DSL. LSM6DSL supports I2C Master - Fast Mode only. Table 8. I2C master timing values I2C Master I2C Fast Mode (min) Unit SCL clock frequency 116.3 0 (400 kHz max) kHz tw(SCLL) SCL clock low time 5.86 1.3 μs tw(SCLH) SCL clock high time 2.74 0.6 ns Data valid time 3.
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LSM6DSL 4.5 Module specifications Absolute maximum ratings Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 9. Absolute maximum ratings Symbol Maximum value Unit Vdd Supply voltage -0.3 to 4.
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Module specifications 4.6 Terminology 4.6.1 Sensitivity LSM6DSL Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor.
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LSM6DSL Functionality 5 Functionality 5.1 Operating modes In the LSM6DSL, the accelerometer and the gyroscope can be turned on/off independently of each other and are allowed to have different ODRs and power modes.
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Functionality 5.4 LSM6DSL Block diagram of filters Figure 5. Block diagram of filters 5.4.1 Block diagrams of the gyroscope filters The gyroscope filtering configuration for both Mode 1 (for User Interface (UI) and Electronic Image Stabilization (EIS) functionality) and Mode 2 is shown in Figure 6. Figure 6. Gyroscope digital chain - Mode 1 (UI/EIS) and Mode 2 63, , & $'& /3) +3) /3) 2'5B* +3B(1B* )7<3( > @ ),)2 /3) B6(/B* The gyroscope ODR is selectable from 12.5 Hz up to 6.
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LSM6DSL 5.4.2 Functionality Block diagrams of the accelerometer filters In the LSM6DSL, the filtering chain for the accelerometer part is composed of the following:  Analog filter (anti-aliasing)  Digital filter (LPF1)  Composite filter Details of the block diagram appear in the following figure. Figure 7.
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Functionality 5.5 LSM6DSL FIFO The presence of a FIFO allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO.
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LSM6DSL 5.5.2 Functionality FIFO mode In FIFO mode (FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 001) data from the output channels are stored in the FIFO until it is full. To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0]) to '000' After this reset command, it is possible to restart FIFO mode by writing FIFO_CTRL5 (0Ah)(FIFO_MODE_[2:0]) to '001'.
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Functionality 5.5.6 LSM6DSL FIFO reading procedure The data stored in FIFO are accessible from dedicated registers (FIFO_DATA_OUT_L (3Eh) and FIFO_DATA_OUT_H (3Fh)) and each FIFO sample is composed of 16 bits. All FIFO status registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh), FIFO_STATUS3 (3Ch), FIFO_STATUS4 (3Dh)) can be read at the start of a reading operation, minimizing the intervention of the application processor.
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LSM6DSL Digital interfaces 6 Digital interfaces 6.1 I2C/SPI interface The registers embedded inside the LSM6DSL may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3. The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the CS line must be tied high (i.e connected to Vdd_IO). Table 10.
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Digital interfaces 6.3 LSM6DSL I2C serial interface The LSM6DSL I2C is a bus slave. The I2C is employed to write the data to the registers, whose content can also be read back. The relevant I2C terminology is provided in the table below. Table 12.
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LSM6DSL Digital interfaces The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged. Table 12 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 13.
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Digital interfaces 6.4 LSM6DSL SPI bus interface The LSM6DSL SPI is a bus slave. The SPI allows writing and reading the registers of the device. The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO. Figure 9. Read and write protocol (in mode 3) &6 63& 6', ', ', ', ', ', ', ', ', 5: $' $' $' $' $' $' $' 6'2 '2 '2 '2 '2 '2 '2 '2 '2 CS is the serial port enable and it is controlled by the SPI master.
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LSM6DSL 6.4.1 Digital interfaces SPI read Figure 10. SPI read protocol (in mode 3) &6 63& 6', 5: $' $' $' $' $' $' $' 6'2 '2 '2 '2 '2 '2 '2 '2 '2 The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode).
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Digital interfaces 6.4.2 LSM6DSL SPI write Figure 12. SPI write protocol (in mode 3) &6 63& 6', ', ', ', ', ', ', ', ', 5: $' $' $' $' $' $' $' The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1 -7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode).
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LSM6DSL 6.4.3 Digital interfaces SPI read in 3-wire mode A 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial interface mode selection). Figure 14. SPI read protocol in 3-wire mode (in mode 3) &6 63& 6', 2 '2 '2 '2 '2 '2 '2 '2 '2 5: $' $' $' $' $' $' $' The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode).
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Application hints LSM6DSL 7 Application hints 7.1 LSM6DSL electrical connections in Mode 1 Figure 15. LSM6DSL electrical connections in Mode 1 &6 6&/ 6'$ 0RGH +267 6'2 6$ 723 9,(: 6'[ 6&[ ,17 & *1' 9'',2 1& , & 63, Z 1& *1' *1' RU 9'',2 /60 '6/ 9GG ,17 9'' & Q) , & FRQILJXUDWLRQ *1' 9GGB,2 5SX 9GGB,2 Q) 5SX 6&/ *1' 6'$ 3XOO XS WR EH DGGHG 5SX N2KP 1. Leave pin electrically unconnected and soldered to PCB.
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LSM6DSL 7.2 Application hints LSM6DSL electrical connections in Mode 2 Figure 16. LSM6DSL electrical connections in Mode 2 6'2 6$ &6 6&/ 6'$ 0RGH , & 63, Z 723 9,(: 06'$ 06&/ /60 '6/ 0'5'< ,17 9GG 0DVWHU , & 9'' /60 '60 ([WHUQDO /60 '60 VHQVRUV & *1' *1' 9'',2 1& 1& ,17 +267 Q) *1' , & FRQILJXUDWLRQ 9GGB,2 & 9GGB,2 5SX Q) *1' 5SX 6&/ 6'$ 3XOO XS WR EH DGGHG 5SX N2KP 1.
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Name Mode 1 function Mode 2 function Pin status Mode 2 SDO SPI 4-wire interface serial data output (SDO) SPI 4-wire interface serial data output (SDO) Default: Input without pull-up. Pull-up is enabled if bit SIM = 1 (SPI 3-wire) in reg 12h. Default: Input without pull-up. Pull-up is enabled if bit SIM = 1 (SPI 3-wire) in reg 12h.
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pin# Name 13 SCL SDA 14 Mode 1 function Mode 2 function Pin status Mode 1 Pin status Mode 2 I2C serial clock (SCL) / SPI serial I2C serial clock (SCL) / SPI serial port clock (SPC) port clock (SPC) Input without pull-up Input without pull-up I2C serial data (SDA) / SPI serial I2C serial data (SDA) / SPI serial data input (SDI) / 3-wire interface data input (SDI) / 3-wire interface serial data output (SDO) serial data output (SDO) Input without pull-up Input without pull-up LSM6DSL Table 18.
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Register mapping 8 LSM6DSL Register mapping The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses. Table 19.
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LSM6DSL Register mapping Table 19.
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Register mapping LSM6DSL Table 19.
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LSM6DSL Register mapping Table 19.
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Register description 9 LSM6DSL Register description The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface. 9.1 FUNC_CFG_ACCESS (01h) Enable embedded functions register (r/w). Table 20. FUNC_CFG_ACCESS register FUNC_ CFG_EN 0(1) FUNC_ CFG_EN_B 0(1) 0(1) 0(1) 0(1) 0(1) 1.
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LSM6DSL 9.3 Register description SENSOR_SYNC_RES_RATIO (05h) Sensor synchronization resolution ratio (r/w) Table 25. SENSOR_SYNC_RES_RATIO register 0 (1) 0 (1) 0(1) 0(1) 0(1) 0(1) RR_1 RR_0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 26. SENSOR_SYNC_RES_RATIO register description RR_[1:0] 9.
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Register description 9.5 LSM6DSL FIFO_CTRL2 (07h) FIFO control register (r/w). Table 29. FIFO_CTRL2 register TIMER_PEDO TIMER_PEDO _FIFO_EN _FIFO_DRDY 0(1) 0(1) FIFO_ TEMP_EN FTH10 FTH_9 FTH_8 1. This bit must be set to ‘0’ for the correct operation of the device. Table 30. FIFO_CTRL2 register description TIMER_PEDO _FIFO_EN Enable pedometer step counter and timestamp as 4th FIFO data set.
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LSM6DSL 9.6 Register description FIFO_CTRL3 (08h) FIFO control register (r/w). Table 31. FIFO_CTRL3 register 0(1) 0(1) DEC_FIFO DEC_FIFO DEC_FIFO DEC_FIFO DEC_FIFO DEC_FIFO _GYRO2 _GYRO1 _GYRO0 _XL2 _XL1 _XL0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 32. FIFO_CTRL3 register description DEC_FIFO_GYRO [2:0] DEC_FIFO_XL [2:0] Gyro FIFO (first data set) decimation setting. Default: 000 For the configuration setting, refer to Table 33.
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Register description 9.7 LSM6DSL FIFO_CTRL4 (09h) FIFO control register (r/w). Table 35. FIFO_CTRL4 register STOP_ ONLY_HIGH ON_ _DATA FTH DEC_DS4 _FIFO2 DEC_DS4 _FIFO1 DEC_DS4 _FIFO0 DEC_DS3 _FIFO2 DEC_DS3 _FIFO1 DEC_DS3 _FIFO0 Table 36. FIFO_CTRL4 register description Enable FIFO threshold level use. Default value: 0. STOP_ON_FTH (0: FIFO depth is not limited; 1: FIFO depth is limited to threshold level) 8-bit data storage in FIFO.
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LSM6DSL 9.8 Register description FIFO_CTRL5 (0Ah) FIFO control register (r/w). Table 39. FIFO_CTRL5 register 0(1) ODR_ FIFO_3 ODR_ FIFO_2 ODR_ FIFO_1 ODR_ FIFO_0 FIFO_ MODE_2 FIFO_ MODE_1 FIFO_ MODE_0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 40. FIFO_CTRL5 register description ODR_FIFO_[3:0] FIFO_MODE_[2:0] FIFO ODR selection, setting FIFO_MODE also. Default: 0000 For the configuration setting, refer to Table 41.
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Register description 9.9 LSM6DSL DRDY_PULSE_CFG_G (0Bh) DataReady configuration register (r/w). Table 43. DRDY_PULSE_CFG_G register DRDY_ PULSED 1. 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) INT2_ WRIST_TILT This bit must be set to ‘0’ for the correct operation of the device. Table 44. DRDY_PULSE_CFG_G register description DRDY_PULSED Enable pulsed DataReady mode. Default value: 0 (0: DataReady latched mode. Returns to 0 only after output data have been read; 1: DataReady pulsed mode.
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LSM6DSL 9.11 Register description INT2_CTRL (0Eh) INT2 pad control register (r/w). Each bit in this register enables a signal to be carried through INT2. The pad’s output will supply the OR combination of the selected signals. Table 47. INT2_CTRL register INT2_STEP INT2_STEP_ INT2_ INT2_ _DELTA COUNT_OV FULL_FLAG FIFO_OVR INT2_ FTH INT2_ DRDY _TEMP INT2_ DRDY_G INT2_ DRDY_XL Table 48.
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Register description 9.13 LSM6DSL CTRL1_XL (10h) Linear acceleration sensor control register 1 (r/w). Table 50. CTRL1_XL register ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 FS_XL1 FS_XL0 LPF1_BW_ SEL BW0_XL Table 51. CTRL1_XL register description ODR_XL [3:0] Output data rate and power mode selection. Default value: 0000 (see Table 52). FS_XL [1:0] Accelerometer full-scale selection. Default value: 00.
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LSM6DSL 9.14 Register description CTRL2_G (11h) Angular rate sensor control register 2 (r/w). Table 53. CTRL2_G register ODR_G3 ODR_G2 ODR_G1 ODR_G0 FS_G1 FS_G0 FS_125 0(1) 1. This bit must be set to ‘0’ for the correct operation of the device. Table 54. CTRL2_G register description ODR_G [3:0] Gyroscope output data rate selection. Default value: 0000 (Refer to Table 55) FS_G [1:0] Gyroscope full-scale selection.
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Register description 9.15 LSM6DSL CTRL3_C (12h) Control register 3 (r/w). Table 56. CTRL3_C register BOOT BDU H_LACTIVE PP_OD SIM IF_INC BLE SW_RESET Table 57. CTRL3_C register description 62/114 BOOT Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) BDU Block Data Update. Default value: 0 (0: continuous update; 1: output registers not updated until MSB and LSB have been read) H_LACTIVE Interrupt activation level.
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LSM6DSL 9.16 Register description CTRL4_C (13h) Control register 4 (r/w). Table 58. CTRL4_C register DEN_ XL_EN SLEEP INT2_on_ DEN_DRDY INT1 _INT1 DRDY_ MASK I2C_disable LPF1_SEL_G 0(1) 1. This bit must be set to ‘0’ for the correct operation of the device. Table 59. CTRL4_C register description DEN_XL_EN Extend DEN functionality to accelerometer sensor. Default value: 0 (0: disabled; 1: enabled) SLEEP Gyroscope sleep mode enable.
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Register description LSM6DSL Table 62.
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LSM6DSL 9.18 Register description CTRL6_C (15h) Angular rate sensor control register 6 (r/w). Table 65. CTRL6_C register TRIG_EN LVL_EN LVL2_EN XL_HM_MODE USR_ OFF_W 0(1) FTYPE_1 FTYPE_0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 66. CTRL6_C register description TRIG_EN DEN data edge-sensitive trigger enable. Refer to Table 67. LVL_EN DEN data level-sensitive trigger enable. Refer to Table 67. LVL2_EN DEN level-sensitive latched enable. Refer to Table 67.
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Register description 9.19 LSM6DSL CTRL7_G (16h) Angular rate sensor control register 7 (r/w). Table 69. CTRL7_G register G_HM_MODE HP_EN_G HPM1_G HPM0_G 0(1) ROUNDING_ STATUS 0(1) 0(1) 1. This bit must be set to ‘0’ for the correct operation of the device. Table 70. CTRL7_G register description High-performance operating mode disable for gyroscope(1). Default: 0 G_HM_MODE (0: high-performance operating mode enabled; 1: high-performance operating mode disabled) 9.
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LSM6DSL Register description Table 73. Accelerometer bandwidth selection HP_SLOPE_ XL_EN LPF2_XL_EN LPF1_BW_SEL HPCF_XL[1:0] INPUT_ COMPOSITE Bandwidth 0 - - ODR/2 1 - - ODR/4 0 00 0 (low-pass path)(1) 1 1 (high-pass path)(2) - 01 - 10 ODR/50 1 (low noise) 0 (low latency) ODR/9 11 ODR/400 00 ODR/4 01 - ODR/100 10 0 11 ODR/100 ODR/9 ODR/400 1. The bandwidth column is related to LPF1 if LPF2_XL_EN = 0 or to LPF2 if LPF2_XL_EN = 1. 2.
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Register description 9.22 LSM6DSL CTRL10_C (19h) Control register 10 (r/w). Table 76. CTRL10_C register WRIST_ TILT_EN 0(1) TIMER_ EN PEDO_ EN TILT_ EN FUNC_EN PEDO_RST SIGN_ _STEP MOTION_EN 1. This bit must be set to ‘0’ for the correct operation of the device. Table 77. CTRL10_C register description WRIST_TILT_EN Enable wrist tilt algorithm(1)(2). Default value: 0 (0: wrist tilt algorithm disabled; 1: wrist tilt algorithm enabled) TIMER_EN Enable timestamp count.
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LSM6DSL Register description Table 79. MASTER_CONFIG register description DRDY_ON_ INT1 Manage the Master DRDY signal on INT1 pad. Default: 0 (0: disable Master DRDY on INT1; 1: enable Master DRDY on INT1) DATA_VALID_ SEL_FIFO Selection of FIFO data-valid signal.
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Register description 9.25 LSM6DSL TAP_SRC (1Ch) Tap source register (r). Table 82. TAP_SRC register 0 TAP_IA SINGLE_ TAP DOUBLE_ TAP_SIGN TAP X_TAP Y_TAP Table 83. TAP_SRC register description 70/114 TAP_IA Tap event detection status. Default: 0 (0: tap event not detected; 1: tap event detected) SINGLE_TAP Single-tap event status. Default value: 0 (0: single tap event not detected; 1: single tap event detected) DOUBLE_TAP Double-tap event detection status.
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LSM6DSL 9.26 Register description D6D_SRC (1Dh) Portrait, landscape, face-up and face-down source register (r) Table 84. D6D_SRC register DEN_ DRDY D6D_IA ZH ZL YH YL XH XL Table 85. D6D_SRC register description DEN_ DRDY DEN data-ready signal. It is set high when data output is related to the data coming from a DEN active condition.(1) D6D_ IA Interrupt active for change position portrait, landscape, face-up, face-down.
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Register description 9.28 LSM6DSL OUT_TEMP_L (20h), OUT_TEMP_H (21h) Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement. Table 88. OUT_TEMP_L register Temp7 Temp6 Temp5 Temp15 Temp14 Temp13 Temp4 Temp3 Temp2 Temp1 Temp0 Temp9 Temp8 Table 89. OUT_TEMP_H register Temp12 Temp11 Temp10 Table 90. OUT_TEMP register description Temp[15:0] 9.
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LSM6DSL 9.31 Register description OUTY_L_G (24h) Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement. Data are according to the full-scale and ODR settings (CTRL2_G (11h)) of the gyro user interface. Table 95. OUTY_L_G register D7 D6 D5 D4 D3 D2 D1 D0 Table 96. OUTY_L_G register description D[7:0] 9.
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Register description 9.34 LSM6DSL OUTZ_H_G (27h) Angular rate sensor Yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement. Data are according to the full-scale and ODR settings (CTRL2_G (11h)) of the gyro user interface. Table 101. OUTZ_H_G register D15 D14 D13 D12 D11 D10 D9 D8 Table 102. OUTZ_H_G register description D[15:8] 9.
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LSM6DSL 9.38 Register description OUTY_H_XL (2Bh) Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s complement. Table 109. OUTY_H_G register D15 D14 D13 D12 D11 D10 D9 D8 Table 110. OUTY_H_G register description D[15:8] 9.39 Y-axis linear acceleration value (MSbyte) OUTZ_L_XL (2Ch) Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s complement. Table 111.
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Register description 9.42 LSM6DSL SENSORHUB2_REG (2Fh) Second byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operations configurations (for external sensors from x = 0 to x = 3). Table 117. SENSORHUB2_REG register SHub2_7 SHub2_6 SHub2_5 SHub2_4 SHub2_3 SHub2_2 SHub2_1 SHub2_0 Table 118. SENSORHUB2_REG register description SHub2_[7:0] Second byte associated to external sensors 9.
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LSM6DSL 9.46 Register description SENSORHUB6_REG (33h) Sixth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 125. SENSORHUB6_REG register SHub6_7 SHub6_6 SHub6_5 SHub6_4 SHub6_3 SHub6_2 SHub6_1 SHub6_0 Table 126. SENSORHUB6_REG register description SHub6_[7:0] 9.
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Register description 9.50 LSM6DSL SENSORHUB10_REG (37h) Tenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 133. SENSORHUB10_REG register SHub10_7 SHub10_6 SHub10_5 SHub10_4 SHub10_3 SHub10_2 SHub10_1 SHub10_0 Table 134. SENSORHUB10_REG register description SHub10_[7:0] Tenth byte associated to external sensors 9.
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LSM6DSL 9.54 Register description FIFO_STATUS2 (3Bh) FIFO status control register (r). For a proper reading of the register, it is recommended to set the BDU bit in CTRL3_C (12h) to 1. Table 141. FIFO_STATUS2 register WaterM OVER_RUN FIFO_ FULL_ SMART FIFO_ EMPTY 0 DIFF_ FIFO_10 DIFF_ FIFO_9 DIFF_ FIFO_8 Table 142. FIFO_STATUS2 register description WaterM FIFO watermark status. The watermark is set through bits FTH_[7:0] in FIFO_CTRL1 (06h).
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Register description 9.56 LSM6DSL FIFO_STATUS4 (3Dh) FIFO status control register (r). For a proper reading of the register, it is recommended to set the BDU bit in CTRL3_C (12h) to 1. Table 145. FIFO_STATUS4 register 0 0 0 0 0 0 FIFO_ PATTERN_9 FIFO_ PATTERN_8 Table 146. FIFO_STATUS4 register description FIFO_ PATTERN_[9:8] 9.57 Word of recursive pattern read at the next reading. FIFO_DATA_OUT_L (3Eh) FIFO data output register (r).
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LSM6DSL 9.59 Register description TIMESTAMP0_REG (40h) Timestamp first (least significant) byte data output register (r). The value is expressed as a 24-bit word and the bit resolution is defined by setting the value in WAKE_UP_DUR (5Ch). Table 151. TIMESTAMP0_REG register TIMESTA MP0_7 TIMESTA MP0_6 TIMESTA MP0_5 TIMESTA MP0_4 TIMESTA MP0_3 TIMESTA MP0_2 TIMESTA MP0_1 TIMESTA MP0_0 Table 152. TIMESTAMP0_REG register description TIMESTAMP0_[7:0] 9.
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Register description 9.62 LSM6DSL STEP_TIMESTAMP_L (49h) Step counter timestamp information register (r). When a step is detected, the value of TIMESTAMP_REG1 register is copied in STEP_TIMESTAMP_L. Table 157. STEP_TIMESTAMP_L register STEP_ TIMESTA MP_L_7 STEP_ TIMESTA MP_L_6 STEP_ TIMESTA MP_L_5 STEP_ TIMESTA MP_L_4 STEP_ TIMESTA MP_L_3 STEP_ TIMESTA MP_L_2 STEP_ TIMESTA MP_L_1 STEP_ TIMESTA MP_L_0 Table 158. STEP_TIMESTAMP_L register description STEP_TIMESTAMP_L[7:0] 9.
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LSM6DSL 9.65 Register description STEP_COUNTER_H (4Ch) Step counter output register (r). Table 163. STEP_COUNTER_H register STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO STEP_CO UNTER_H UNTER_H UNTER_H UNTER_H UNTER_H UNTER_H UNTER_H UNTER_H _7 _6 _5 _4 _3 _2 _1 _0 Table 164. STEP_COUNTER_H register description STEP_COUNTER_H_[7:0] 9.66 Step counter output (MSbyte) SENSORHUB13_REG (4Dh) Thirteenth byte associated to external sensors.
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Register description 9.69 LSM6DSL SENSORHUB16_REG (50h) Sixteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 171. SENSORHUB16_REG register SHub16_7 SHub16_6 SHub16_5 SHub16_4 SHub16_3 SHub16_2 SHub16_1 SHub16_0 Table 172. SENSORHUB16_REG register description SHub16_[7:0] 9.
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LSM6DSL 9.72 Register description FUNC_SRC1 (53h) Significant motion, tilt, step detector, hard/soft-iron and sensor hub interrupt source register (r). Table 177. FUNC_SRC1 register STEP_ COUNT _DELTA _IA SIGN_ MOTION_IA TILT_IA STEP_ STEP_ DETECTED OVERFLOW HI_ FAIL SI_END_ OP SENSOR HUB_ END_OP Table 178. FUNC_SRC1 register description Pedometer step recognition on delta time status.
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Register description 9.74 LSM6DSL WRIST_TILT_IA (55h) Wrist tilt interrupt source register (r). Table 181. WRIST_TILT_IA register WRIST_ TILT_IA_ Xpos WRIST_ TILT_IA_ Xneg WRIST_ TILT_IA_ Ypos WRIST_ TILT_IA_ Yneg WRIST_ TILT_IA_ Zpos WRIST_ TILT_IA_ Zneg 0 0 Table 182. WRIST_TILT_IA register description Absolute Wrist Tilt event detection status on X-positive axis.
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LSM6DSL 9.75 Register description TAP_CFG (58h) Enables interrupt and inactivity functions, configuration of filtering and tap recognition functions (r/w). Table 183. TAP_CFG register INTERRUPTS SLOPE INACT_EN1 INACT_EN0 TAP_X_EN TAP_Y_EN TAP_Z_EN _ENABLE _FDS LIR Table 184. TAP_CFG register description INTERRUPTS _ENABLE Enable basic interrupts (6D/4D, free-fall, wake-up, tap, inactivity). Default 0. (0: interrupt disabled; 1: interrupt enabled) Enable inactivity function.
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Register description 9.76 LSM6DSL TAP_THS_6D (59h) Portrait/landscape position and tap function threshold register (r/w). Table 185. TAP_THS_6D register D4D_EN SIXD_THS SIXD_THS TAP_THS 1 0 4 TAP_THS 3 TAP_THS 2 TAP_THS 1 TAP_THS 0 Table 186. TAP_THS_6D register description 4D orientation detection enable. Z-axis position detection is disabled. D4D_EN Default value: 0 (0: enabled; 1: disabled) SIXD_THS[1:0] TAP_THS[4:0] Threshold for 4D/6D function.
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LSM6DSL 9.78 Register description WAKE_UP_THS (5Bh) Single and double-tap function threshold register (r/w). Table 190. WAKE_UP_THS register SINGLE_ DOUBLE _TAP 0 WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0 Table 191. WAKE_UP_THS register description 9.79 SINGLE_DOUBLE_TAP Single/double-tap event enable. Default: 0 (0: only single-tap event enabled; 1: both single and double-tap events enabled) WK_THS[5:0] Threshold for wakeup.
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Register description 9.80 LSM6DSL FREE_FALL (5Dh) Free-fall function duration setting register (r/w). Table 194. FREE_FALL register FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0 Table 195. FREE_FALL register description FF_DUR[4:0] Free-fall duration event. Default: 0 For the complete configuration of the free fall duration, refer to FF_DUR5 in WAKE_UP_DUR (5Ch) configuration FF_THS[2:0] Free fall threshold setting. Default: 000 For details refer to Table 196. Table 196.
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LSM6DSL 9.81 Register description MD1_CFG (5Eh) Functions routing on INT1 register (r/w). Table 197. MD1_CFG register INT1_ INACT_ STATE INT1_ SINGLE_ TAP INT1_WU INT1_FF INT1_ DOUBLE_ TAP INT1_6D INT1_TILT INT1_ TIMER Table 198. MD1_CFG register description INT1_INACT_ STATE Routing on INT1 of inactivity mode. Default: 0 (0: routing on INT1 of inactivity disabled; 1: routing on INT1 of inactivity enabled) Single-tap recognition routing on INT1.
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Register description 9.82 LSM6DSL MD2_CFG (5Fh) Functions routing on INT2 register (r/w). Table 199. MD2_CFG register INT2_ INACT_ STATE INT2_ SINGLE_ TAP INT2_WU INT2_FF INT2_ DOUBLE_ TAP INT2_6D INT2_TILT INT2_ IRON Table 200. MD2_CFG register description INT2_INACT_ STATE Routing on INT2 of inactivity mode. Default: 0 (0: routing on INT2 of inactivity disabled; 1: routing on INT2 of inactivity enabled) Single-tap recognition routing on INT2.
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LSM6DSL 9.83 Register description MASTER_CMD_CODE (60h) Table 201. MASTER_CMD_CODE register MASTER_ MASTER_ MASTER_ MASTER_ MASTER_ MASTER_ MASTER_ MASTER_ CMD_ CMD_ CMD_ CMD_ CMD_ CMD_ CMD_ CMD_ CODE0 CODE1 CODE2 CODE3 CODE4 CODE5 CODE6 CODE7 Table 202. MASTER_CMD_CODE register description MASTER_CMD_ CODE[7:0] 9.84 Master command code used for stamping for sensor sync. Default: 0 SENS_SYNC_SPI_ERROR_CODE (61h) Table 203.
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Register description 9.87 LSM6DSL OUT_MAG_RAW_Y_L (68h) External magnetometer raw data (r). Table 209. OUT_MAG_RAW_Y_L register D7 D6 D5 D4 D3 D2 D1 D0 Table 210. OUT_MAG_RAW_Y_L register description D[7:0] 9.88 Y-axis external magnetometer value (LSbyte) OUT_MAG_RAW_Y_H (69h) External magnetometer raw data (r). Table 211. OUT_MAG_RAW_Y_H register D15 D14 D13 D12 D11 D10 D9 D8 Table 212. OUT_MAG_RAW_Y_H register description D[15:8] 9.
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LSM6DSL 9.91 Register description X_OFS_USR (73h) Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is internally added to the acceleration value measured on the X-axis. Table 217. X_OFS_USR register X_OFS_ USR_7 X_OFS_ USR_6 X_OFS_ USR_5 X_OFS_ USR_4 X_OFS_ USR_3 X_OFS_ USR_2 X_OFS_ USR_1 X_OFS_ USR_0 Table 218. X_OFS_USR register description X_OFS_USR_ [7:0] 9.
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Embedded functions register mapping 10 LSM6DSL Embedded functions register mapping The tables given below provide a list of the first (A) and second (B) bank registers related to the embedded functions available in the device and the corresponding addresses. The embedded functions registers of bank A are accessible when FUNC_CFG_EN is set to ‘1’ in FUNC_CFG_ACCESS (01h). The embedded functions registers of bank B are accessible when both FUNC_CFG_EN and FUNC_CFG_EN_B set to ‘1’ in FUNC_CFG_ACCESS (01h).
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LSM6DSL Embedded functions register mapping Table 223.
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Embedded functions registers description - Bank A LSM6DSL 11 Embedded functions registers description - Bank A Note: All modifications of the content of the embedded functions registers have to be performed with the device in power-down mode. 11.1 SLV0_ADD (02h) I2C slave address of the first external sensor (Sensor1) register (r/w). Table 225. SLV0_ADD register Slave0_ add6 Slave0_ add5 Slave0_ add4 Slave0_ add3 Slave0_ add2 Slave0_ add1 Slave0_ add0 rw_0 Table 226.
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LSM6DSL Embedded functions registers description - Bank A Table 230. SLAVE0_CONFIG register description Slave0_rate[1:0] Decimation of read operation on Sensor1 starting from the sensor hub trigger. Default value: 00 (00: no decimation 01: update every 2 samples 10: update every 4 samples 11: update every 8 samples) Aux_sens_on[1:0] Number of external sensors to be read by sensor hub.
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Embedded functions registers description - Bank A 11.6 LSM6DSL SLAVE1_CONFIG (07h) Second external sensor (Sensor2) configuration register (r/w). Table 235. SLAVE1_CONFIG register Slave1_ rate1 Slave1_ rate0 write_once 0(1) 0(1) Slave1_ numop2 Slave1_ numop1 Slave1_ numop0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 236. SLAVE1_CONFIG register description Slave1_rate[1:0] Decimation of read operation on Sensor2 starting from the sensor hub trigger.
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LSM6DSL 11.9 Embedded functions registers description - Bank A SLAVE2_CONFIG (0Ah) Third external sensor (Sensor3) configuration register (r/w). Table 241. SLAVE2_CONFIG register Slave2_ rate1 Slave2_ rate0 0(1) 0(1) 0(1) Slave2_ numop2 Slave2_ numop1 Slave2_ numop0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 242. SLAVE2_CONFIG register description Decimation of read operation on Sensor3 starting from the sensor hub trigger.
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Embedded functions registers description - Bank A 11.12 LSM6DSL SLAVE3_CONFIG (0Dh) Fourth external sensor (Sensor4) configuration register (r/w). Table 247. SLAVE3_CONFIG register Slave3_ rate1 Slave3_ rate0 0(1) 0(1) 0(1) Slave3_ numop2 Slave3_ numop1 Slave3_ numop0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 248. SLAVE3_CONFIG register description 11.13 Slave3_rate[1:0] Decimation of read operation on Sensor4 starting from the sensor hub trigger.
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LSM6DSL 11.15 Embedded functions registers description - Bank A SM_THS (13h) Significant motion configuration register (r/w). Table 253. SM_THS register SM_THS_ SM_THS_ SM_THS_ SM_THS_ SM_THS_ SM_THS_ SM_THS_ SM_THS_ 7 6 5 4 3 2 1 0 Table 254. SM_THS register description SM_THS[7:0] 11.16 Significant motion threshold. Default value: 00000110 PEDO_DEB_REG (14h) Table 255.
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Embedded functions registers description - Bank A 11.18 LSM6DSL MAG_SI_XX (24h) Soft-iron matrix correction register (r/w). Table 259. MAG_SI_XX register MAG_SI_ XX_7 MAG_SI_ XX_6 MAG_SI_ XX_5 MAG_SI_ XX_4 MAG_SI_ XX_3 MAG_SI_ XX_2 MAG_SI_ XX_1 MAG_SI_ XX_0 Table 260. MAG_SI_XX register description MAG_SI_XX_[7:0] Soft-iron correction row1 col1 coefficient(1). Default value: 00001000 1. Value is expressed in sign-module format. 11.19 MAG_SI_XY (25h) Soft-iron matrix correction register (r/w).
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LSM6DSL 11.22 Embedded functions registers description - Bank A MAG_SI_YY (28h) Soft-iron matrix correction register (r/w). Table 267. MAG_SI_YY register MAG_SI_ YY_7 MAG_SI_ YY_6 MAG_SI_ YY_5 MAG_SI_ YY_4 MAG_SI_ YY_3 MAG_SI_ YY_2 MAG_SI_ YY_1 MAG_SI_ YY_0 Table 268. MAG_SI_YY register description MAG_SI_YY_[7:0] Soft-iron correction row2 col2 coefficient(1). Default value: 00001000 1. Value is expressed in sign-module format. 11.23 MAG_SI_YZ (29h) Soft-iron matrix correction register (r/w).
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Embedded functions registers description - Bank A 11.26 LSM6DSL MAG_SI_ZZ (2Ch) Soft-iron matrix correction register (r/w). Table 275. MAG_SI_ZZ register MAG_SI_ ZZ_7 MAG_SI_ ZZ_6 MAG_SI_ ZZ_5 MAG_SI_ ZZ_4 MAG_SI_ ZZ_3 MAG_SI_ ZZ_2 MAG_SI_ ZZ_1 MAG_SI_ ZZ_0 Table 276. MAG_SI_ZZ register description MAG_SI_ZZ_[7:0] Soft-iron correction row3 col3 coefficient(1). Default value: 00001000 1. Value is expressed in sign-module format. 11.
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LSM6DSL 11.30 Embedded functions registers description - Bank A MAG_OFFY_H (30h) Offset for Y-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement. Table 283. MAG_OFFY_H register MAG_OFF MAG_OFF MAG_OFF MAG_OFF MAG_OFF MAG_OFF MAG_OFF MAG_OFF Y_H_7 Y_H_6 Y_H_5 Y_H_4 Y_H_3 Y_H_2 Y_H_1 Y_H_0 Table 284. MAG_OFFY_H register description MAG_OFFY_H_[7:0] 11.31 Offset for Y-axis hard-iron compensation.
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Embedded functions registers description - Bank B LSM6DSL 12 Embedded functions registers description - Bank B 12.1 A_WRIST_TILT_LAT (50h) Absolute Wrist Tilt latency register (r/w). Table 289. A_WRIST_TILT_LAT register WRIST_TILT WRIST_TILT WRIST_TILT WRIST_TILT WRIST_TILT WRIST_TILT WRIST_TILT WRIST_TILT _ TIMER7 _ TIMER6 _ TIMER5 _ TIMER4 _ TIMER3 _ TIMER2 _ TIMER1 _ TIMER0 Table 290. A_WRIST_TILT_LAT register description Absolute wrist tilt latency parameters. 1 LSB = 40 ms.
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LSM6DSL 13 Soldering information Soldering information The LGA package is compliant with the ECOPACK®, RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Land pattern and soldering recommendations are available at www.st.com/mems.
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Package information 14 LSM6DSL Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 14.1 LGA-14 package information Figure 17. LGA-14 2.5x3x0.
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LSM6DSL 14.2 Package information LGA-14 packing information Figure 18. Carrier tape information for LGA-14 package Figure 19.
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Package information LSM6DSL Figure 20. Reel information for carrier tape of LGA-14 package 7 PP PLQ $FFHVV KROH DW VORW ORFDWLRQ % & $ 1 ' )XOO UDGLXV * PHDVXUHG DW KXE 7DSH VORW LQ FRUH IRU WDSH VWDUW PP PLQ ZLGWK Table 295. Reel dimensions for carrier tape of LGA-14 package Reel dimensions (mm) 112/114 A (max) 330 B (min) 1.5 C 13 ±0.25 D (min) 20.2 N (min) 60 G 12.4 +2/-0 T (max) 18.
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LSM6DSL 15 Revision history Revision history Table 296. Document revision history Date 03-May-2017 29-Sep-2017 Revision Changes 6 Updated Section 4.4.
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LSM6DSL IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.