Datasheet

M24C16, M24C08, M24C04, M24C02, M24C01 DC and AC parameters
Doc ID 5067 Rev 16 23/39
Table 15. AC characteristics at 400 kHz (I
2
C Fast-mode) (M24Cxx-W, M24Cxx-R,
M24Cxx-F)
Test conditions specified in either Tabl e 6 , Ta ble 7 or Table 8 and Table 13
Symbol Alt. Parameter Min.
(1)
1. All values are referred to V
IL
(max) and V
IH
(min).
Max.
(1)
Unit
f
C
f
SCL
Clock frequency 400 kHz
t
CHCL
t
HIGH
Clock pulse width high 600 ns
t
CLCH
t
LOW
Clock pulse width low 1300 ns
t
QL1QL2
(2)
2. Characterized only, not tested in production.
t
F
SDA (out) fall time 20
(3)
3. With C
L
= 10 pF.
120 ns
t
XH1XH2
t
R
Input signal rise time
(4)
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C
< 400 kHz.
(4)
ns
t
XL1XL2
t
F
Input signal fall time
(4) (4)
ns
t
DXCX
t
SU:DAT
Data in set up time 100 ns
t
CLDX
t
HD:DAT
Data in hold time 0 ns
t
CLQX
t
DH
Data out hold time 100 ns
t
CLQV
(5)(6)
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3V
CC
or
0.7V
CC
, assuming that R
bus
× C
bus
time constant is within the values specified in Figure 5.
t
AA
Clock low to next data valid (access time) 200 900 ns
t
CHDL
t
SU:STA
Start condition setup time 600 ns
t
DLCL
t
HD:STA
Start condition hold time 600 ns
t
CHDH
t
SU:STO
Stop condition set up time 600 ns
t
DHDL
t
BUF
Time between Stop condition and next Start
condition
1300 ns
t
W
t
WR
Write time 5 ms