Datasheet

ManualsBrandsST ManualsEEPROMEEPROM 4 k x 8 Bit SO-8

December 2009 Doc ID 4578 Rev 17 1/38

M24C32-W

M24C32-R M24C32-F

32 Kbit serial I²C bus EEPROM

Features

■ Supports the I

C bus modes:

– 400 kHz Fast-mode

– 100 kHz Standard-mode

■ Single supply voltages:

– 2.5 V to 5.5 V (M24C32-W)

– 1.8 V to 5.5 V (M24C32-R)

– 1.7 V to 5.5 V (M24C32-F)

■ Write Control input

■ Byte and Page Write

■ Random and Sequential Read modes

■ Self-timed programming cycle

■ Automatic address incrementing

■ Enhanced ESD/latch-up protection

■ More than 1 Million write cycles

■ More than 40-year data retention

■ Packages

– SO8, TSSOP8, UFDFPN8 packages:

ECOPACK2

(RoHS-compliant and

Halogen-free)

– PDIP8 package:

ECOPACK1

(RoHS-compliant)

PDIP8 (BN)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

UFDFPN8 (MB)

2 × 3 mm (MLP)

www.st.com

Summary of content (38 pages)

PAGE 1
M24C32-W M24C32-R M24C32-F 32 Kbit serial I²C bus EEPROM Features ■ Supports the I2C bus modes: – 400 kHz Fast-mode – 100 kHz Standard-mode ■ Single supply voltages: – 2.5 V to 5.5 V (M24C32-W) – 1.8 V to 5.5 V (M24C32-R) – 1.7 V to 5.
PAGE 2
Contents M24C32-W M24C32-R M24C32-F Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.
PAGE 3
M24C32-W M24C32-R M24C32-F Contents 5 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Part numbering . . . . . . . . . . . . . .
PAGE 4
List of tables M24C32-W M24C32-R M24C32-F List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. 4/38 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
M24C32-W M24C32-R M24C32-F List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DIP, SO, TSSOP and UFDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . .
PAGE 6
Description 1 M24C32-W M24C32-R M24C32-F Description The M24C32-W, M24C32-R and M24C32-F devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 4096 × 8 bits. Figure 1. Logic diagram 6## % % 3$! - XXX 3#, 7# 633 !) F I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition.
PAGE 7
M24C32-W M24C32-R M24C32-F Table 1. Description Signal names Signal name Function Direction E0, E1, E2 Chip Enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage VSS Ground Figure 2. DIP, SO, TSSOP and UFDFPN connections % % % 633 6## 7# 3#, 3$! !) F 1. See Package mechanical data section for package dimensions, and how to identify pin-1.
PAGE 8
Signal description M24C32-W M24C32-R M24C32-F 2 Signal description 2.1 Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated).
PAGE 9
M24C32-W M24C32-R M24C32-F 2.5 Signal description VSS ground VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 7, Table 8 and Table 9).
PAGE 10
Signal description M24C32-W M24C32-R M24C32-F Maximum RP value versus bus parasitic capacitance (C) for an I2C bus Figure 4. Bus line pull-up resistor (k ) 100 10 4 kΩ When tLOW = 1.3 µs (min value for fC = 400 kHz), the Rbus × Cbus time constant must be below the 400 ns time constant line represented on the left. R bu s × C bu s = Here Rbus × Cbus = 120 ns 40 VCC Rbus 0n s SCL I²C bus master M24xxx SDA 1 30 pF 10 100 Bus line capacitor (pF) Cbus 1000 ai14796b Figure 5.
PAGE 11
M24C32-W M24C32-R M24C32-F Table 2. Signal description Device select code Device type identifier(1) Device select code Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. Table 3. b15 Table 4.
PAGE 12
Memory organization 3 M24C32-W M24C32-R M24C32-F Memory organization The memory is organized as shown in Figure 6. Figure 6.
PAGE 13
M24C32-W M24C32-R M24C32-F 4 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization.
PAGE 14
Device operation 4.5 M24C32-W M24C32-R M24C32-F Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is 1010b.
PAGE 15
M24C32-W M24C32-R M24C32-F Figure 7.
PAGE 16
Device operation 4.6 M24C32-W M24C32-R M24C32-F Write operations Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data Byte. Writing to the memory may be inhibited if Write Control (WC) is driven high.
PAGE 17
M24C32-W M24C32-R M24C32-F Figure 8.
PAGE 18
Device operation Figure 9. M24C32-W M24C32-R M24C32-F Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK Returned YES NO Next operation is addressing the memory YES Send address and receive ACK ReStart NO Stop Start condition YES Data for the Write operation Device select with RW = 1 Continue the Write operation Continue the Random Read operation AI01847d 4.
PAGE 19
M24C32-W M24C32-R M24C32-F Device operation Figure 10.
PAGE 20
Device operation 4.10 M24C32-W M24C32-R M24C32-F Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address. 4.11 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition.
PAGE 21
M24C32-W M24C32-R M24C32-F 5 Initial delivery state Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 6 Maximum rating Stressing the device outside the ratings listed in Table 6 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied.
PAGE 22
DC and AC parameters 7 M24C32-W M24C32-R M24C32-F DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7.
PAGE 23
M24C32-W M24C32-R M24C32-F DC and AC parameters Figure 11. AC test measurement I/O waveform Input Levels Input and Output Timing Reference Levels 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI00825B Table 11. Input parameters Symbol Parameter Test condition Min. Max. Unit CIN Input capacitance (SDA) 8 pF CIN Input capacitance (other pins) 6 pF 200 k ZWCL(1) WC input impedance VIN < 0.3VCC 50 ZWCH(1) WC input impedance VIN > 0.
PAGE 24
DC and AC parameters Table 13. Symbol M24C32-W M24C32-R M24C32-F DC characteristics (M24xxx-W, device grade 3) Test condition (in addition to those in Table 7) Parameter Min. Max. Unit VIN = VSS or VCC device in Standby mode ±2 µA ILI Input leakage current (SCL, SDA, E2, E1, E0) ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC ±2 µA ICC Supply current (Read) 2.5 V < VCC < 5.5 V, fc = 400 kHz 2 mA (1) 5 mA 10 µA –0.45 0.
PAGE 25
M24C32-W M24C32-R M24C32-F Table 15. Symbol DC and AC parameters DC characteristics (M24xxx-F) Test condition (in addition to those in Table 9) Parameter Min. Max. Unit ILI Input leakage current (SCL, SDA, E2, E1, E0) VIN = VSS or VCC device in Standby mode ±2 µA ILO Output leakage current SDA Hi-Z, external voltage applied on SDA: VSS or VCC ±2 µA ICC Supply current (Read) VCC =1.7 V, fc = 400 kHz 0.8 mA ICC0 Supply current (Write) During tW, 1.7 V < VCC < 2.
PAGE 26
DC and AC parameters Table 16. M24C32-W M24C32-R M24C32-F AC characteristics Test conditions specified in Table 7, Table 8 and Table 9 Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH Clock pulse width high 600 ns tCLCH tLOW Clock pulse width low 1300 ns tQL1QL2(1) tXH1XH2 tF tR Parameter SDA (out) fall time Min. 20 (2) Max.
PAGE 27
M24C32-W M24C32-R M24C32-F DC and AC parameters Figure 12.
PAGE 28
Package mechanical data 8 M24C32-W M24C32-R M24C32-F Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B 1.
PAGE 29
M24C32-W M24C32-R M24C32-F Package mechanical data Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 18. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ Min 1.75 Max 0.0689 A1 0.10 A2 1.25 b 0.28 0.48 0.0110 0.0189 c 0.17 0.23 0.0067 0.
PAGE 30
Package mechanical data M24C32-W M24C32-R M24C32-F Figure 15. TSSOP8 – 8 lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 19. TSSOP8 – 8 lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ. Min. A Max. 0.050 0.150 0.800 1.050 b 0.190 c 0.090 1.000 CP Max. 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.
PAGE 31
M24C32-W M24C32-R M24C32-F Package mechanical data Figure 16. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package outline e D b L1 L3 E E2 L A D2 ddd A1 UFDFPN-01 1. Drawing is not to scale. 2. The central pad (the E2 × D2 area in the above illustration) is internally pulled to VSS. It should not be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 20.
PAGE 32
Part numbering 9 M24C32-W M24C32-R M24C32-F Part numbering Table 21. Ordering information scheme Example: M24C32– W MN 6 T P /P Device type M24 = I2C serial access EEPROM Device function C32– = 32 Kbit (4096 x 8) Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.
PAGE 33
M24C32-W M24C32-R M24C32-F Table 22. Part numbering Available M24C32 products (package, voltage range, temperature grade) M24C32-F 1.7 V to 5.5 V M24C32-R 1.8 V to 5.5 V M24C32-W 2.5 V to 5.
PAGE 34
Revision history 10 M24C32-W M24C32-R M24C32-F Revision history Table 23. 34/38 Document revision history Date Revision Changes 22-Dec-1999 2.3 TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo, PackageMechData). 28-Jun-2000 2.4 TSSOP8 package data corrected 31-Oct-2000 2.5 References to Temperature Range 3 removed from Ordering Information Voltage range -S added, and range -R removed from text and tables throughout. 20-Apr-2001 2.
PAGE 35
M24C32-W M24C32-R M24C32-F Table 23. Revision history Document revision history (continued) Date 29-Jun-2006 03-Jul-2006 17-Oct-2006 27-Apr-2007 27-Nov-2007 Revision Changes 7 Document converted to new ST template. M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed. M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added. Section 2.3: Chip Enable (E0, E1, E2) and Section 2.4: Write Control (WC) modified, Section 2.
PAGE 36
Revision history M24C32-W M24C32-R M24C32-F Table 23. Document revision history (continued) Date Revision Changes 18-Dec-2007 12 Added Section 2.6.2: Power-up conditions, updated Section 2.6.3: Device reset, and Section 2.6.4: Power-down conditions in Section 2.6: Supply voltage (VCC). Updated Figure 4: Maximum RP value versus bus parasitic capacitance (C) for an I2C bus. Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6, respectively, in Section 4.
PAGE 37
M24C32-W M24C32-R M24C32-F Table 23. Revision history Document revision history (continued) Date Revision Changes 05-Jan-2009 16 I2C modes supported specified in Features on page 1. Note removed from Table 15: DC characteristics (M24xxx-F). Small text changes. 17 64 and 128 Kbit densities removed. ECOPACK status of packages specified on page 1 and in Table 21: Ordering information scheme. Section 2.6.2: Power-up conditions updated.
PAGE 38
M24C32-W M24C32-R M24C32-F Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.