Datasheet

ManualsBrandsST ManualsEEPROMEEPROM 8 k x 8 Bit SO-8

December 2010 Doc ID 16891 Rev 21 1/43

M24C64-DF

M24C64-W M24C64-R M24C64-F

64 Kbit serial I²C bus EEPROM

Features

■ Compatible with all I

C bus modes:

– 1 MHz Fast-mode Plus

– 400 kHz Fast mode

– 100 kHz Standard mode

■ Memory array:

– 64 Kb (8 Kbytes) of EEPROM

– Page size: 32 bytes

■ M24C64-DF: additional Write lockable Page

(Identification page)

■ Write

– Byte Write within 5 ms

– Page Write within 5 ms

■ Random and Sequential Read modes

■ Write protect of the whole memory array

■ Single supply voltage:

– M24C64-W: 2.5 V to 5.5 V

– M24C64-R: 1.8 V to 5.5 V

– M24C64-xF: 1.7 V to 5.5 V

■ Enhanced ESD/Latch-Up protection

■ More than 1 million Write cycles

■ More than 40-year data retention

■ Packages

– ECOPACK2® (RoHS-compliant and

halogen-free)

– PDIP8 package: ECOPACK1® (RoHS-

compliant)

PDIP8 (BN)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

UFDFPN8

(MB, MC)

WLCSP5 (CS)

www.st.com

Summary of content (43 pages)

PAGE 1
M24C64-DF M24C64-W M24C64-R M24C64-F 64 Kbit serial I²C bus EEPROM Features ■ Compatible with all I2C bus modes: – 1 MHz Fast-mode Plus – 400 kHz Fast mode – 100 kHz Standard mode ■ Memory array: – 64 Kb (8 Kbytes) of EEPROM – Page size: 32 bytes PDIP8 (BN) ■ M24C64-DF: additional Write lockable Page (Identification page) ■ Write – Byte Write within 5 ms – Page Write within 5 ms ■ Random and Sequential Read modes ■ Write protect of the whole memory array ■ Single supply voltage: – M24C64-W: 2.
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Contents M24C64-DF, M24C64-W, M24C64-R, M24C64-F Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Contents 4.16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.17 Read Identification Page (M24C64-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.18 Read the lock status (M24C64-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Initial delivery state . . . . . . .
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List of tables M24C64-DF, M24C64-W, M24C64-R, M24C64-F List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. 4/43 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . .
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Description 1 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Description M24C64-x and M24C64-DF devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 8192 × 8 bits. The M24C64-D also offers an additional page, named the Identification Page (32 bytes) which can be written and (later) permanently locked in Read-only mode.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 1. Description Signal names Signal name Function Direction E0, E1, E2 Chip Enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage VSS Ground Figure 2. 8-pin package connections % % % 633 6## 7# 3#, 3$! !) F 1. See Package mechanical data section for package dimensions, and how to identify pin-1. Figure 3.
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Signal description M24C64-DF, M24C64-W, M24C64-R, M24C64-F 2 Signal description 2.1 Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated).
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F 2.5 Signal description VSS ground VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 7, Table 8 and Table 9).
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Signal description M24C64-DF, M24C64-W, M24C64-R, M24C64-F I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) Figure 5. Bus line pull-up resistor (k ) 100 10 4 kΩ When tLOW = 1.3 µs (min value for fC = 400 kHz), the Rbus × Cbus time constant must be below the 400 ns time constant line represented on the left.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Figure 7. Signal description I2C bus protocol SCL SDA SDA Input Start Condition SCL 1 SDA MSB 2 SDA Change Stop Condition 3 7 8 9 ACK Start Condition SCL 1 SDA MSB 2 3 7 8 9 ACK Stop Condition AI00792B Table 2. Device select code Device type identifier(1) Device select code Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2.
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Memory organization 3 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Memory organization The memory is organized as shown in Figure 8. Figure 8.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F 4 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization.
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Device operation 4.5 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0).
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Figure 9.
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Device operation 4.6 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Write operations Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 10, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data Byte. Each data byte in the memory has a 16-bit (two byte wide) address.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Device operation Figure 10. Write mode sequences with WC = 0 (data write enabled) WC ACK Byte address ACK Byte address ACK Data in Stop Dev Select Start Byte Write ACK R/W WC ACK Dev Select Start Page Write ACK Byte address ACK Byte address ACK Data in 1 Data in 2 R/W WC (cont'd) ACK Data in N Stop Page Write (cont'd) ACK 4.
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Device operation 4.10 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Lock Identification Page (M24C64-D only) The Lock Identification Page instruction (Lock ID) permanently locks the Identification Page in Read-only mode.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Device operation Figure 11.
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Device operation M24C64-DF, M24C64-W, M24C64-R, M24C64-F Figure 12.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F 4.13 Device operation Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address. 4.14 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 12) but without sending a Stop condition.
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Device operation 4.18 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Read the lock status (M24C64-D) The locked/unlocked status of the Identification page can be checked by issuing a specific truncated command [Identification Page Write instruction + one data byte]: this data byte will be acknowledged if the Identification page is unlocked, while it will not be acknowledged if the Identification page is locked.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F 5 Initial delivery state Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 6 Maximum rating Stressing the device outside the ratings listed in Table 6 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied.
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DC and AC parameters 7 M24C64-DF, M24C64-W, M24C64-R, M24C64-F DC and AC parameters This section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 11. Input parameters Parameter(1) Symbol DC and AC parameters Test condition Min. Max. Unit CIN Input capacitance (SDA) 8 pF CIN Input capacitance (other pins) 6 pF ZL(2) Input impedance (E2, E1, E0, WC) VIN < 0.3VCC 30 k ZH(2) Input impedance (E2, E1, E0, WC) VIN > 0.7VCC 500 k 1. Characterized value, not tested in production. 2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition). Table 12.
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DC and AC parameters Table 13.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 14. Symbol DC and AC parameters DC characteristics (M24xxx-R - device grade 6) Test conditions(1) (in addition to those in Table 8 and Table 10) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC ±2 µA 0.8(2) mA fc= 1 MHz(3) 2.5 mA During tW, 1.8 V < VCC < 2.5 V 3(4) mA 1 µA VCC = 1.
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DC and AC parameters Table 15. Symbol M24C64-DF, M24C64-W, M24C64-R, M24C64-F DC characteristics (M24xxx-F) Test conditions(1) (in addition to those in Table 9 and Table 10) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC ±2 µA 0.8(2) mA fc= 1 MHz(3) 2.5 mA During tW, 1.7 V < VCC < 2.5 V 3(4) mA 1 µA VCC = 1.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 16. DC and AC parameters 400 kHz AC characteristics Test conditions (in addition to those in Table 7, Table 8, Table 9 and Table 10) Symbol Alt.
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DC and AC parameters Table 17. M24C64-DF, M24C64-W, M24C64-R, M24C64-F 1 MHz AC characteristics(1) Test conditions specified in Table 7, Table 8 and Table 10 Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tLOW tXH1XH2 tXL1XL2 tQL1QL2 (6) tR tF tF Parameter Min. Max.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F DC and AC parameters Figure 14.
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Package mechanical data 8 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 15. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B 1.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Package mechanical data Figure 16. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 19. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ Min 1.75 Max 0.0689 A1 0.10 A2 1.25 b 0.28 0.48 0.0110 0.0189 c 0.17 0.23 0.
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Package mechanical data M24C64-DF, M24C64-W, M24C64-R, M24C64-F Figure 17. TSSOP8 – 8 lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 20. TSSOP8 – 8 lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ. Min. A Max. 0.050 0.150 0.800 1.050 b 0.190 c 0.090 1.000 CP Max. 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Package mechanical data Figure 18. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package outline 2%6 -" E $ 2%6 -# E B , , B , , 0IN 0IN % % % + + , , ! $ $ DDD ! AI 1. Drawing is not to scale. 2. The central pad (E2 × D2 area in the above illustration) is internally pulled to VSS.
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Package mechanical data M24C64-DF, M24C64-W, M24C64-R, M24C64-F Figure 19. WLCSP-R 5-bump wafer-length chip-scale package outline E $ # E $ETAIL ! % E " ! /RIENTATION REFERENCE /RIENTATION REFERENCE ' ! & ! 3IDE VIEW 7AFER BACK SIDE "UMP SIDE "UMP $ETAIL ! ROTATED BY ! B -3 1. Drawing is not to scale. Table 22. WLCSP-R 5-bump wafer-length chip-scale package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.545 0.455 0.635 0.0215 0.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F 9 Part numbering Part numbering Table 23. Ordering information scheme Example: M24C64–D W MN 6 T P /P Device type M24 = I2C serial access EEPROM Device function C64– = 64 Kbit (8192 x 8) Device family Blank: Without Identification page D: With additional Identification page Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.
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Part numbering M24C64-DF, M24C64-W, M24C64-R, M24C64-F For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 24. Available M24C64 products (package, voltage range, temperature grade) M24C64-F 1.7 V to 5.5 V M24C64-R 1.8 V to 5.5 V M24C64-W 2.5 V to 5.
PAGE 39
M24C64-DF, M24C64-W, M24C64-R, M24C64-F 10 Revision history Revision history Table 26. Document revision history Date Revision Changes 22-Dec-1999 2.3 TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo, PackageMechData). 28-Jun-2000 2.4 TSSOP8 package data corrected 31-Oct-2000 2.5 References to Temperature Range 3 removed from Ordering Information Voltage range -S added, and range -R removed from text and tables throughout. 20-Apr-2001 2.
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Revision history M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 26. Document revision history (continued) Date 29-Jun-2006 03-Jul-2006 17-Oct-2006 27-Apr-2007 27-Nov-2007 40/43 Revision Changes 7 Document converted to new ST template. M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed. M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added. Section 2.3: Chip Enable (E0, E1, E2) and Section 2.4: Write Control (WC) modified, Section 2.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 26. Revision history Document revision history (continued) Date Revision Changes 18-Dec-2007 12 Added Section 2.6.2: Power-up conditions, updated Section 2.6.3: Device reset, and Section 2.6.4: Power-down conditions in Section 2.6: Supply voltage (VCC). Updated Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus). Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6, respectively, in Section 4.
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Revision history M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 26. Document revision history (continued) Date Revision Changes 10-Dec-2009 17 32 and 128 Kbit densities removed. ECOPACK status of packages specified on page 1 and in Table 23: Ordering information scheme. Section 2.6.2: Power-up conditions updated. Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) updated. ECC section removed. tNS modified in Table 23: Input parameters.
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.