Datasheet

ManualsBrandsST ManualsEEPROMEEPROM I²C/Serial 1MB 900ns SO-8

This is information on a product in full production.

October 2017 DocID12943 Rev 14 1/47

M24M01-R M24M01-DF

1-Mbit serial I²C bus EEPROM

Datasheet - production data

Features

• Compatible with all I

C bus modes:

–1 MHz

– 400 kHz

– 100 kHz

• Memory array:

– 1 Mbit (128 Kbyte) of EEPROM

– Page size: 256 byte

– Additional Write lockable page (M24M01-D

order codes)

• Single supply voltage and high speed:

– 1 MHz clock from 1.7 V to 5.5 V

• Write:

– Byte Write within 5 ms

– Page Write within 5 ms

• Operating temperature range:

– from -40 °C up to +85 °C

• Random and sequential Read modes

• Write protect of the whole memory array

• Enhanced ESD/Latch-Up protection

• More than 4 million Write cycles

• More than 200-years data retention

Packages

• SO8 ECOPACK2

• TSSOP8 ECOPACK2

• WLCSP ECOPACK2

• Unsawn wafer (each die is tested)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

WLCSP (CS, CX)

Unsawn wafer

www.st.com

Summary of content (47 pages)

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M24M01-R M24M01-DF 1-Mbit serial I²C bus EEPROM Datasheet - production data Features SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width • Compatible with all I2C bus modes: – 1 MHz – 400 kHz – 100 kHz • Memory array: – 1 Mbit (128 Kbyte) of EEPROM – Page size: 256 byte – Additional Write lockable page (M24M01-D order codes) • Single supply voltage and high speed: – 1 MHz clock from 1.7 V to 5.
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Contents M24M01-R M24M01-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.
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M24M01-R M24M01-DF Contents 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 Read Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 Read the lock status (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . .
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List of tables M24M01-R M24M01-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. 4/47 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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M24M01-R M24M01-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Description 1 M24M01-R M24M01-DF Description The M24M01 is a 1 Mbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 128 K × 8 bits. The M24M01-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24M01-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of –40 °C / +85 °C. The M24M01-D offers an additional page, named the Identification Page (256 byte).
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M24M01-R M24M01-DF Description Figure 2. 8-pin package connections, top view '8 9&& ( :& ( 6&/ 966 6'$ 06 9 1. DU: Don’t use (no signal should be applied on this pin; if connected, must be connected to VSS) 2. See Section 9: Package information for package dimensions, and how to identify pin 1 Figure 3. WLCSP connections (top view, marking side, with balls on the underside) & % $ 9 && 6'$ 6&/ ( :& ( 9 66 '8 06 9 1.
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Signal description M24M01-R M24M01-DF 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus.
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M24M01-R M24M01-DF Signal description 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters).
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Memory organization 3 M24M01-R M24M01-DF Memory organization The memory is organized as shown below. Figure 5.
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M24M01-R M24M01-DF 4 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization.
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Device operation 4.1 M24M01-R M24M01-DF Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high.
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M24M01-R M24M01-DF 4.5 Device operation Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (most significant bit first). Table 2.
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Instructions M24M01-R M24M01-DF 5 Instructions 5.1 Write operations Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 3. Most significant address byte A15 A14 A13 A12 A11 A10 A9 A8 A1 A0 Table 4.
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M24M01-R M24M01-DF 5.1.1 Instructions Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7. Figure 7.
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Instructions 5.1.2 M24M01-R M24M01-DF Page Write The Page Write mode allows up to 256 byte to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, b16-b8, are the same. If more bytes are sent than will fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0.
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M24M01-R M24M01-DF 5.1.3 Instructions Write Identification Page (M24M01-D only) The Identification Page (256 byte) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction.
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Instructions 5.1.6 M24M01-R M24M01-DF Minimizing Write delays by polling on ACK The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is: • Initial condition: a Write cycle is in progress. • Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).
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M24M01-R M24M01-DF Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device internal address counter is incremented by one, to point to the next byte address. For the Read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time.
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Instructions 5.2.1 M24M01-R M24M01-DF Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 5.2.
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M24M01-R M24M01-DF 5.4 Instructions Read the lock status (M24M01-D only) The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked.
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Initial delivery state 6 M24M01-R M24M01-DF Initial delivery state The device is delivered with all the memory array bits and Identification page bits set to 1 (each byte contains FFh).
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M24M01-R M24M01-DF 7 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 5 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol TSTG TLEAD Parameter Min. Max.
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DC and AC parameters 8 M24M01-R M24M01-DF DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 6. Operating conditions (voltage range R) Symbol Min. Max. Unit Supply voltage 1.8 5.5 V TA Ambient operating temperature –40 85 °C fC Operating clock frequency - 1 MHz Min. Max. Unit Supply voltage 1.7 5.
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M24M01-R M24M01-DF DC and AC parameters Table 10. Cycling performance Symbol Ncycle Parameter Write cycle endurance(2) Test condition(1) Max. TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000 Unit Write cycle(3) 1. Cycling performance for products identified by process letter K 2. The write cycle endurance is defined for group of four bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer.
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DC and AC parameters M24M01-R M24M01-DF Table 12. DC characteristics (M24M01-R, device grade 6) Symbol Test conditions (in addition to those in Table 6) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.8 V, fc= 400 kHz - 1(1) VCC = 2.5 V, fc =400 kHz - 1 VCC = 5.5 V, fc =400 kHz - 1.5(2) fc= 1 MHz - 1.
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M24M01-R M24M01-DF DC and AC parameters Table 13. DC characteristics (M24M01-DF, device grade 6) Symbol Test conditions (in addition to those in Table 6) Parameter Min. Max. Unit ILI Input leakage current (E1, E2, SCL, SDA) VIN = VSS or VCC device in Standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.7 V, fc= 400 kHz - 1 mA VCC = 2.5 V, fc =400 kHz - 1 mA VCC = 5.5 V, fc =400 kHz - 1.5 mA fc= 1 MHz - 1.
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DC and AC parameters M24M01-R M24M01-DF Table 14. 400 kHz AC characteristics Symbol Alt. fC fSCL Clock frequency tCHCL tHIGH tCLCH tLOW tQL1QL2(1) tF tXH1XH2 tR Parameter Min. Max.
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M24M01-R M24M01-DF DC and AC parameters Table 15. 1 MHz AC characteristics Symbol Alt. Parameter Min. Max.
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DC and AC parameters M24M01-R M24M01-DF Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz "US LINE PULL UP RESISTOR K K½ 4HE 2 BUS X #BUS TIME CONSTANT MUST BE BELOW THE NS TIME CONSTANT LINE REPRESENTED ON THE LEFT 2 BU S § # BU S (ERE 2BUS § #BUS NS 6## 2BUS NS )£# BUS MASTER 3#, - XXX 3$! P& "US LINE CAPACITOR P& #BUS AI B Figure 13.
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M24M01-R M24M01-DF DC and AC parameters Figure 14.
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Package information 9 M24M01-R M24M01-DF Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. For die information concerning the M24M01 delivered in unsawn wafer, please contact your nearest ST Sales Office. 9.1 TSSOP8 package information Figure 15.
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M24M01-R M24M01-DF Package information Table 16. TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - α 0° - 8° 0° - 8° 1. Values in inches are converted from mm and rounded to four decimal digits.
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Package information 9.2 M24M01-R M24M01-DF SO8N package information Figure 16. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package outline H X ! ! C CCC B E PP *$8*( 3/$1( $ K % % ! , , 62 $B9 1. Drawing is not to scale. Table 17. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package mechanical data Symbol inches(1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.
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M24M01-R M24M01-DF Package information Figure 17. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package recommended footprint [ 2 B62 1B)3B9 1. Dimensions are expressed in millimeters.
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Package information 9.3 M24M01-R M24M01-DF WLCSP8 ultra thin package information Figure 18. WLCSP - 8 balls, 2.578x1.716 mm, 0.5 mm pitch, wafer level chip scale package outline EEE = ; ' H < H ) H ( H H '(7$,/ $ ) DDD 3LQ FRUQHU $ $ [ 723 9,(: * * 3LQ FRUQHU 6,'( 9,(: %27720 9,(: %803 $ HHH = = E [ FFF 0 = ; < GGG 0 = 6($7,1* 3/$1( '(7$,/ $ 527$7(' % 5B:/&63 B0(B9 1. Drawing is not to scale. 2.
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M24M01-R M24M01-DF Package information Table 18. WLCSP - 8 balls, 2.578x1.716 mm, 0.5 mm pitch, wafer level chip scale mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max G - 0.789 - - 0.0311 - aaa - 0.11 - - 0.0043 - bbb - 0.11 - - 0.0043 - ccc - 0.11 - - 0.0043 - ddd - 0.06 - - 0.0024 - eee - 0.06 - - 0.0024 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 19. WLCSP - 8 balls, 2.578x1.
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Package information 9.4 M24M01-R M24M01-DF WLCSP8 package information Figure 20. WLCSP- 8-bump, without BSC, 2.578 x 1.716 mm, wafer level chip scale package outline EEE = ' ; H < ) H '(7$,/ $ H H H ( ) DDD $ $ ; 723 9,(: * 3,1 &251(5 6,'( 9,(: * %27720 9,(: %803 $ HHH ] = E ; FFF 0 = ; < 6($7,1* 3/$1( GGG 0 = '(7$,/ $ 527$7(' ( B:/&63 5B 0BQR%6&B0(B9 1. Drawing is not to scale. 2.
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M24M01-R M24M01-DF Package information Table 19. WLCSP- 8-bump, without BSC, 2.578 x 1.716 mm, wafer level chip scale package outline (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max e2 - 0.500 - - 0.0197 - e3 - 0.500 - - 0.0197 - F - 0.425 - - 0.0167 - G - 0.789 - - 0.0311 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.060 - - 0.0024 - eee - 0.060 - - 0.0024 - 1.
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Package information M24M01-R M24M01-DF Figure 21. WLCSP- 8-bump, with BSC, 2.578 x 1.716 mm, wafer level chip scale package outline EEE = ' ; H < ) H '(7$,/ $ H H H ( ) DDD $ $ ; $ 6,'( 9,(: 723 9,(: * 3,1 &251(5 * %27720 9,(: %803 $ HHH ] = E ; FFF 0 = ; < 6($7,1* 3/$1( GGG 0 = '(7$,/ $ 527$7(' ( B:/&63 5B 0B%6&B0(B9 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the bump. Table 20.
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M24M01-R M24M01-DF Package information Table 20. WLCSP- 8-bump, with BSC, 2.578 x 1.716 mm, wafer level chip scale package outline (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max e3 - 0.500 - - 0.0197 - F - 0.425 - - 0.0167 - G - 0.789 - - 0.0311 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.060 - - 0.0024 - eee - 0.060 - - 0.0024 - 1.
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Ordering information 10 M24M01-R M24M01-DF Ordering information Table 21. Ordering information scheme Example: M24M01 -D R MN 6 T P /K Device type M24 = I2C serial access EEPROM Device function M01 = 1 Mbit (128 K x 8 bit) Device family Blank = Without Identification page D = With Identification page Operating voltage R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.
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M24M01-R M24M01-DF Ordering information Table 22. Ordering information scheme (unsawn wafer)(1) Example: M24M01 - D F K W 20 I / 90 Device type M24 = I2C serial access EEPROM Device function M01 = 1Mbit (128 K x 8 bit) Device family D = With Identification page Operating voltage F = VCC = 1.7 V to 5.5 V Process K = F8H Delivery form W = Unsawn wafer Wafer thickness 20 = Non-backlapped wafer Wafer testing I = Inkless test Device grade 90 = -40°C to 85°C 1.
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Ordering information M24M01-R M24M01-DF Engineering samples Parts marked as ES or E are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences deriving from such use. In no event, will ST be liable for the customer using of these engineering samples in production. ST’s quality department must be contacted prior to any decision to use these engineering samples to run qualification activity.
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M24M01-R M24M01-DF 11 Revision history Revision history Table 23. Document revision history Date 02-May-2011 23-Apr-2012 26-Sep-2012 Revision Changes 8 Updated Features on page 1. Updated Figure 3: WLCSP8 connections (bumps side view), Figure 5: Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz and Figure 6: Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz.
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Revision history M24M01-R M24M01-DF Table 23.
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M24M01-R M24M01-DF IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.