M48T02 M48T12 5.
Contents M48T02, M48T12 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.
M48T02, M48T12 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC characteristics . . . . . . . . . . . . . . . . . . .
List of figures M48T02, M48T12 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. 4/25 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . .
M48T02, M48T12 1 Description Description The M48T02/12 TIMEKEEPER® RAM is a 2 Kb x 8 non-volatile static RAM and real-time clock which is pin and functional compatible with the DS1642. A special 24-pin, 600 mil DIP CAPHAT™ package houses the M48T02/12 silicon with a quartz crystal and a long life lithium button cell to form a highly integrated battery-backed memory and real-time clock solution.
Description Figure 2. M48T02, M48T12 DIP connections A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 3.
M48T02, M48T12 2 Operation modes Operation modes As Figure 3 on page 6 shows, the static memory array and the quartz controlled clock oscillator of the M48T02/12 are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 7F8h-7FFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour BCD format.
Operation modes M48T02, M48T12 The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access. Figure 4.
M48T02, M48T12 2.2 Operation modes WRITE mode The M48T02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle.
Operation modes Table 4.
M48T02, M48T12 Figure 7.
Clock operations 3 Clock operations 3.1 Reading the clock M48T02, M48T12 Updates to the TIMEKEEPER® registers should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, the seventh bit in the control register.
M48T02, M48T12 Table 5.
Clock operations M48T02, M48T12 '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
M48T02, M48T12 Figure 8. Clock operations Crystal accuracy across temperature ppm 20 0 -20 -40 ΔF = -0.038 ppm (T - T )2 ± 10% 0 F C2 -60 T0 = 25 °C -80 -100 0 Figure 9.
Clock operations 3.5 M48T02, M48T12 VCC noise and negative going transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.
M48T02, M48T12 4 Maximum ratings Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6.
DC and AC parameters 5 M48T02, M48T12 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7.
M48T02, M48T12 Table 9. DC and AC parameters DC characteristics Symbol ILI ILO(2) ICC ICC1(3) ICC2 (3) Test condition(1) Parameter Input leakage current Output leakage current Supply current Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA Outputs open 80 mA E = VIH 3 mA E = VCC – 0.2 V 3 mA Supply current (standby) TTL Supply current (standby) CMOS Min VIL Input low voltage –0.3 0.8 V VIH Input high voltage 2.2 VCC + 0.3 V VOL Output low voltage IOL = 2.1 mA 0.
DC and AC parameters Table 10. M48T02, M48T12 Power down/up AC characteristics Parameter(1) Symbol Min Max Unit tPD E or W at VIH before power down 0 - µs tF(2) VPFD (max) to VPFD (min) VCC fall time 300 - µs tFB(3) VPFD (min) to VSS VCC fall time 10 - µs tR VPFD (min) to VPFD (max) VCC rise time 0 - µs tRB VSS to VPFD (min) VCC rise time 1 - µs trec E or W at VIH before power-up 2 - ms 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.
M48T02, M48T12 6 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline A2 A1 B1 B A L e1 C eA e3 D N E 1 PCDIP Note: Drawing is not to scale.
Part numbering 7 M48T02, M48T12 Part numbering Table 13. Ordering information scheme Example: M48T 02 –70 PC 1 Device type M48T Supply voltage and write protect voltage 02 = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V 12 = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V Speed –70 = 70 ns (M48T02/12) –150 = 150 ns (M48T02/12) –200 = 200 ns (M48T02/12)(1) Package PC = PCDIP24 Temperature range 1 = 0 to 70 °C Shipping method blank = ECOPACK® package, tubes 1. Not recommended for new design.
M48T02, M48T12 8 Environmental information Environmental information Figure 14. Recycling symbols This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
Revision history 9 M48T02, M48T12 Revision history Table 14. 24/25 Document revision history Date Revision Jul-2000 1.0 Changes First issue 13-Jul-2000 1.1 trec change (Table 10) 07-May-2001 2.0 Reformatted; temp. / voltage info. added to tables (Table 8, 9, 3, 4, 10, 11) 14-May-2001 2.1 Note added to clock calibration section; table footnote correction (Table 2) 16-Jul-2001 2.2 Basic formatting / content changes (cover page, Table 8, 9) 20-May-2002 2.
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