Datasheet

ManualsBrandsST ManualsEmbedded Processors & Controllers8 Bit Shift Latch Register Serial to Serial / Parallel DIP 90ns

M54HC4094

M74HC4094

February 1993

8 BIT SIPO SHIFT LATCH REGISTER (3-STATE)

B1R

(Plastic Package)

ORDER CODES :

M54HC4094F1R M74HC4094M1R

M74HC4094B1R M74HC4094C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

DESCRIPTION

.HIGH SPEED

MAX

= 73 MHz (TYP.) AT V

=5V

.LOW POWER DISSIPATION

=4µA (MAX.) AT T

=25°C

.HIGH NOISE IMMUNITY

NIH

NIL

=28%V

(MIN.)

.OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.SYMMETRICAL OUTPUT IMPEDANCE

|=I

= 4 mA (MIN.)

.BALANCEDPROPAGATION DELAYS

PLH

PHL

.WIDE OPERATING VOLTAGE RANGE

(OPR) = 2 V TO 6 V

.PIN AND FUNCTION COMPATIBLE

WITH 4094B

The M54/74HC4094 is a high speed CMOS 8 BIT

SIPOSHIFTLATCH REGISTERfabricated withsili-

con gate C

MOS technology.

It has the same high speed performance of LSTTL

combined with true CMOS low power consumption.

This device consists of an 8-bit shift register and an

8-bit latch with 3-state output buffer. Data is shifted

serially through the shift register on the positive

going transition of the clock input signal. The output

of the last stage (Qs) can be used to cascade sev-

eral devices.

Dataon the Qsoutput is transferred toa second out-

put (Qs’) on the following negative transition of the

clockinput signal. The data of eachstage of the shift

on the negative going transition of the STROBE

input signal. When the STROBE input is held high,

datapropagates through thelatchto a3-state output

buffer.

This buffer is enabled when OUTPUT ENABLE

input is taken high. All inputs are equipped with pro-

tectioncircuits against static discharge and transient

excess voltage.

1/12

Summary of content (12 pages)

PAGE 1
M54HC4094 M74HC4094 8 BIT SIPO SHIFT LATCH REGISTER (3-STATE) . . . . . . . . HIGH SPEED fMAX = 73 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.
PAGE 2
M54/M74HC4094 LOGIC DIAGRAM LOGIC DIAGRAM 2/12
PAGE 3
M54/ M74HC4094 TRUTH TABLE CK PARALLEL OUTPUT SERIAL OUTPUT OE ST SI H H L Q1 L Qn Qn-1 Qs Q7 Qs’ NC H H H H Qn-1 Q7 NC H L L X X X NC Z NC Z Q7 Q7 NC NC H X X NC NC NC Qs L X X Z Z NC Qs X: Don’t Care Z: High Impedance NC: No Change INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 SYMBOL STROBE 2 SERIAL IN 3 4, 5, 6, 7, 14, 13, 12, 11 9, 10 CLOCK Q1 to Q7 15 OE 8 16 GND V CC QS Q’S IEC LOGIC SYMBOL NAME AND FUNCTION Strobe Input Serial Input
PAGE 4
M54/M74HC4094 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit VCC VI Supply Voltage DC Input Voltage -0.5 to +7 -0.5 to VCC + 0.5 V V VO DC Output Voltage -0.5 to VCC + 0.
PAGE 5
M54/ M74HC4094 DC SPECIFICATIONS Test Conditions Symbol VIH V IL Parameter High Level Input Voltage Low Level Input Voltage Value VCC (V) TA = 25 oC 54HC and 74HC Min. Typ. Max. 2.0 1.5 1.5 1.5 4.5 6.0 3.15 4.2 3.15 4.2 3.15 4.2 High Level Output Voltage 0.5 0.5 0.5 4.5 1.35 1.35 1.35 2.0 4.5 6.0 4.5 VOL Low Level Output Voltage 6.0 2.0 4.5 6.0 4.5 6.0 II IOZ ICC Input Leakage Current 3 State Output Off State Current Quiescent Supply Current 1.8 1.8 Unit V 2.0 6.
PAGE 6
M54/M74HC4094 AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns) Test Conditions Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CLOCK - Qn) tPLH tPHL Propagation Delay Time (CLOCK - QS, Q’S) tPLH tPHL Propagation Delay Time (STROBE - Qn) tPZL tPZH 3 State Output Enable Time tPHZ tPLZ 3 State Output Disable Time fMAX Maximum Clock Frequency tW(H) tW(L) Minimum Pulse Width tW(L) Minimum Pulse Width ts ts th Value o VCC (V) TA = 25 C
PAGE 7
M54/ M74HC4094 SWITCHING CHARACTERISTICS TEST WAVEFORM TEST WAVEFORM ICC (Opr.) C PD CALCULATION CPD is to be calculated with the following formula by using the measured value of ICC (Opr.) in the test circuit opposite. ICC (Opr) CPD= fIN × VCC In determining the typical value of CPD, a relatively high frequency of 1 MHz was applied to fIN, in order to eliminate any error caused by the quiescent supply current.
PAGE 8
M54/M74HC4094 Plastic DIP16 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.51 B 0.77 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.
PAGE 9
M54/ M74HC4094 Ceramic DIP16/1 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 20 0.787 B 7 0.276 D E 3.3 0.130 0.38 e3 0.015 17.78 0.700 F 2.29 2.79 0.090 0.110 G 0.4 0.55 0.016 0.022 H 1.17 1.52 0.046 0.060 L 0.22 0.31 0.009 0.012 M 0.51 1.27 0.020 0.050 N P Q 10.3 7.8 8.05 5.08 0.406 0.307 0.317 0.
PAGE 10
M54/M74HC4094 SO16 (Narrow) MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.004 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8° (max.
PAGE 11
M54/ M74HC4094 PLCC20 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 9.78 10.03 0.385 0.395 B 8.89 9.04 0.350 0.356 D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 E 7.37 8.38 0.290 0.330 e 1.27 0.050 e3 5.08 0.200 F 0.38 0.015 G 0.101 0.004 M 1.27 0.050 M1 1.14 0.
PAGE 12
M54/M74HC4094 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice.