Datasheet

ManualsBrandsST ManualsEEPROMEEPROM SPI 2 k x 8 Bit SO-8

1/40October 2004

M95160

M95080

16Kbit and 8Kbit Serial SPI Bus EEPROM

With High Speed Clock

FEATURES SUMMARY

■ Compatible with SPI Bus Serial Interface

(Positive Clock SPI Modes)

■ Single Supply Voltage:

– 4.5 to 5.5V for M95xxx

– 2.5 to 5.5V for M95xxx-W

– 1.8 to 5.5V for M95xxx-R

■ High Speed

– 10MHz Clock Rate, 5ms Write Time

■ Status Register

■ Hardware Protection of the Status Register

■ BYTE and PAGE WRITE (up to 32 Bytes)

■ Self-Timed Programming Cycle

■ Adjustable Size Read-Only EEPROM Area

■ Enhanced ESD Protection

■ More than 1 Million Erase/Write Cycles

■ More than 40-Year Data Retention

Table 1. Product List

Figure 1. Packages

Reference Part Number

M95160

M95160-W

M95160-R

M95080

M95080-W

M95080-R

PDIP8 (BN)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

TSSOP8 (DS)

3x3mm² body size (MSOP)

UFDFPN8 (MB)

2x3mm² (MLP)

Summary of content (41 pages)

PAGE 1
M95160 M95080 16Kbit and 8Kbit Serial SPI Bus EEPROM With High Speed Clock FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Single Supply Voltage: – 4.5 to 5.5V for M95xxx – 2.5 to 5.5V for M95xxx-W – 1.8 to 5.
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M95160, M95080 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . .
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M95160, M95080 Figure 7. Write Enable (WREN) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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M95160, M95080 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 18.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 33 Table 24. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 33 Figure 19.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 34 Table 25.
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M95160, M95080 SUMMARY DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized as 2048 x 8 bit (M95160), and 1024 x 8 bit (M95080). The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2. and Figure 2.. The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold (HOLD).
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M95160, M95080 SIGNAL DESCRIPTION During all operations, V CC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 14. to Table 18.). These signals are described next. Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D).
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M95160, M95080 CONNECTING TO THE SPI BUS These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low. All output data bytes are shifted out of the device, most significant bit first.
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M95160, M95080 SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5.
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M95160, M95080 OPERATING FEATURES Power-up When the power supply is turned on, V CC rises from VSS to VCC. During this time, the Chip Select (S) must be allowed to follow the V CC voltage. It must not be allowed to float, but should be connected to VCC via a suitable pull-up resistor. As a built in safety feature, Chip Select (S) is edge sensitive as well as level sensitive. After Powerup, the device does not become selected until a falling edge has first been detected on Chip Select (S).
PAGE 10
M95160, M95080 Status Register Figure 6. shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP1, BP0 bits.
PAGE 11
M95160, M95080 MEMORY ORGANIZATION The memory is organized as shown in Figure 6.. Figure 6.
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M95160, M95080 INSTRUCTIONS Each instruction starts with a single-byte code, as summarized in Table 5.. If an invalid instruction is sent (one not contained in Table 5.), the device automatically deselects itself. 12/40 Table 5.
PAGE 13
M95160, M95080 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 7., to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. Figure 7.
PAGE 14
M95160, M95080 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 9..
PAGE 15
M95160, M95080 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
PAGE 16
M95160, M95080 If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used. (BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
PAGE 17
M95160, M95080 Read from Memory Array (READ) As shown in Figure 11., to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q).
PAGE 18
M95160, M95080 Write to Memory Array (WRITE) As shown in Figure 12., to send this instruction to the device, Chip Select (S) is first driven Low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input data. In the case of Figure 12.
PAGE 19
M95160, M95080 Figure 13. Page Write (WRITE) Sequence S 0 1 2 3 4 5 6 7 8 20 21 22 23 24 25 26 27 28 29 30 31 9 10 C Instruction 16-Bit Address 15 14 13 D 3 2 Data Byte 1 1 0 7 6 5 4 3 2 0 1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 D 7 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte N 1 0 6 5 4 3 2 1 0 AI01796D Note: Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
PAGE 20
M95160, M95080 POWER-UP AND DELIVERY STATE Power-up State After Power-up, the device is in the following state: – Standby Power mode – deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started). – not in the Hold Condition – the Write Enable Latch (WEL) is reset to 0 – Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous powerdown (they are non-volatile bits).
PAGE 21
M95160, M95080 MAXIMUM RATING Stressing the device outside the ratings listed in Table 8. may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8.
PAGE 22
M95160, M95080 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure- ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 9.
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M95160, M95080 Table 13. Capacitance Symbol COUT CIN Parameter Test Condition Max. Unit VOUT = 0V 8 pF Input Capacitance (D) VIN = 0V 8 pF Input Capacitance (other pins) VIN = 0V 6 pF Max. Unit VIN = VSS or VCC ±2 µA S = VCC, VOUT = VSS or VCC ±2 µA C = 0.1VCC/0.9VCC at 5MHz, VCC = 5 V, Q = open, Previous Product 2 4 mA C = 0.1VCC/0.
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M95160, M95080 Table 15. DC Characteristics (M95xxx, Device Grade 3) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC ICC1 Supply Current Supply Current (Standby Power mode) Test Condition Min. Max. Unit VIN = VSS or VCC ±2 µA S = VCC, VOUT = VSS or VCC ±2 µA C = 0.1VCC/0.9VCC at 2 MHz, VCC = 5 V, Q = open, Previous Product 2 4 mA C = 0.1VCC/0.
PAGE 25
M95160, M95080 Table 17. DC Characteristics (M95xxx-W, Device Grade 3) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current Test Condition Min. Max. Unit VIN = VSS or VCC ±2 µA S = VCC, VOUT = VSS or VCC ±2 µA C = 0.1VCC/0.9VCC at 2 MHz, VCC = 2.5 V, Q = open, Previous Product 1 5 mA C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open, Present Product 2 2 mA S = VCC, VCC = 2.
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M95160, M95080 Table 19. AC Characteristics (M95xxx, Device Grade 6) Test conditions specified in Table 12. and Table 9. Max.4 Min.5 Max.5 Unit D.C. 5 D.C. 10 MHz Alt. fC fSCK Clock Frequency tSLCH tCSS1 S Active Setup Time 90 15 ns tSHCH tCSS2 S Not Active Setup Time 90 15 ns tSHSL tCS S Deselect Time 100 40 ns tCHSH tCSH S Active Hold Time 90 25 ns S Not Active Hold Time 90 15 ns tCHSL Parameter Min.
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M95160, M95080 Table 20. AC Characteristics (M95xxx, Device Grade 3) Test conditions specified in Table 12. and Table 9. Min.4 Max.4 Min.5 Max.5 Unit Clock Frequency D.C. 2 D.C. 5 MHz tCSS1 S Active Setup Time 200 90 ns tSHCH tCSS2 S Not Active Setup Time 200 90 ns tSHSL tCS S Deselect Time 200 100 ns tCHSH tCSH S Active Hold Time 200 90 ns S Not Active Hold Time 200 90 ns Symbol Alt.
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M95160, M95080 Table 21. AC Characteristics (M95xxx-W, Device Grade 6) Test conditions specified in Table 12. and Table 10. Min.4 Max.4 Min.5 Max.5 Unit Clock Frequency D.C. 2 D.C. 5 MHz tCSS1 S Active Setup Time 200 90 ns tSHCH tCSS2 S Not Active Setup Time 200 90 ns tSHSL tCS S Deselect Time 200 100 ns tCHSH tCSH S Active Hold Time 200 90 ns S Not Active Hold Time 200 90 ns Symbol Alt.
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M95160, M95080 Table 22. AC Characteristics (M95xxx-W, Device Grade 3) Test conditions specified in Table 12. and Table 10. Min.4 Max.4 Min.5 Max.5 Unit Clock Frequency D.C. 2 D.C. 5 MHz tCSS1 S Active Setup Time 200 90 ns tSHCH tCSS2 S Not Active Setup Time 200 90 ns tSHSL tCS S Deselect Time 200 100 ns tCHSH tCSH S Active Hold Time 200 90 ns S Not Active Hold Time 200 90 ns Symbol Alt.
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M95160, M95080 Table 23. AC Characteristics (M95xxx-R) Test conditions specified in Table 12. and Table 11. Min.4,5 Max.4,5 Unit Clock Frequency D.C. 2 MHz tCSS1 S Active Setup Time 200 ns tSHCH tCSS2 S Not Active Setup Time 200 ns tSHSL tCS S Deselect Time 200 ns tCHSH tCSH S Active Hold Time 200 ns S Not Active Hold Time 200 ns Symbol Alt.
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M95160, M95080 Figure 15. Serial Input Timing tSHSL S tCHSL tSLCH tCHSH tSHCH C tDVCH tCHCL tCHDX D Q tCLCH LSB IN MSB IN High Impedance AI01447C Figure 16.
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M95160, M95080 Figure 17. Output Timing S tCH C tCLQV tCLQX tCLQV tCL tSHQZ tCLQX LSB OUT Q tQLQH tQHQL D ADDR.
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M95160, M95080 PACKAGE MECHANICAL Figure 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B Note: Drawing is not to scale. Table 24. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data mm inches Symb. Typ. Min. A Max. Typ. Min. 5.33 A1 Max. 0.210 0.38 0.015 A2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.
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M95160, M95080 Figure 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline h x 45˚ A2 A C B ddd e D 8 E H 1 α A1 L SO-A Note: Drawing is not to scale. Table 25. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Mechanical Data millimeters inches Symbol Typ Min Max A 1.35 A1 Min Max 1.75 0.053 0.069 0.10 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.
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M95160, M95080 Figure 20. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline e D b L1 L3 E E2 L A D2 ddd A1 UFDFPN-01 Note: 1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 26.
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M95160, M95080 Figure 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8AM Note: Drawing is not to scale. Table 27. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data millimeters inches Symbol Typ Min A 0.050 0.150 0.800 1.050 b 0.190 c 0.090 A2 Typ Min 1.200 A1 1.000 CP Max 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.
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M95160, M95080 Figure 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8BM Note: Drawing is not to scale. Table 28. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data millimeters inches Symbol Typ Min A Max Min 1.100 A1 0.050 0.150 0.750 0.950 b 0.250 c A2 Typ 0.850 Max 0.0433 0.0020 0.0059 0.0295 0.0374 0.400 0.0098 0.0157 0.130 0.230 0.0051 0.
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M95160, M95080 PART NUMBERING Table 29. Ordering Information Scheme Example: M95160 – W MN 6 T P /W Device Type M95 = SPI serial access EEPROM Device Function 160 = 16 Kbit (2048 x 8) 080 = 8 Kbit (1024 x 8) Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V Package BN = PDIP8 MN = SO8 (150 mil width) DW 2 = TSSOP8 DS3 = TSSOP8 (3x3mm body size, MSOP) MB = MLP8 (UFDFPN8) Device Grade 6 = Industrial temperature range, –40 to 85 °C.
PAGE 39
M95160, M95080 REVISION HISTORY Table 31. Document Revision History Date Rev. Description of Revision 19-Jul-2001 1.0 Document written from previous M95640/320/160/080 datasheet 06-Feb-2002 1.1 Announcement made of planned upgrade to 10MHz clock for the 5V, –40 to 85°C, range 18-Oct-2002 1.2 TSSOP8 (3x3mm body size, MSOP8) package added 04-Nov-2002 1.3 New products, identified by the process letter W, added 13-Nov-2002 1.
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M95160, M95080 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.
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