M95256-W M95256-R M95256-DR M95256-DF 256-Kbit serial SPI bus EEPROM with high-speed clock Datasheet − production data Features ■ Compatible with the Serial Peripheral Interface (SPI) bus ■ Memory array – 256 Kb (32 Kbytes) of EEPROM – Page size: 64 bytes SO8 (MN) 150 mil width ■ Write – Byte Write within 5 ms – Page Write within 5 ms ■ Additional Write lockable page (Identification page) ■ Write Protect: quarter, half or whole memory array ■ High-speed clock: 20 MHz ■ Single supply voltage:
Contents M95256-W M95256-R M95256-DR M95256-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.
M95256-W M95256-R M95256-DR M95256-DF 6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.
List of tables M95256-W M95256-R M95256-DR M95256-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. 4/53 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write-protected block size . . . . . .
M95256-W M95256-R M95256-DR M95256-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description 1 M95256-W M95256-R M95256-DR M95256-DF Description The M95256 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 32768 x 8 bits, accessed through the SPI bus. The M95256-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95256-R and M95256-DR can operate with a supply voltage from 1.8 V to 5.5 V, and the M95256-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
M95256-W M95256-R M95256-DR M95256-DF Figure 2. Description 8-pin package connections (top view) M95xxx S Q W VSS 1 2 3 4 VCC HOLD C D 8 7 6 5 AI01790D 1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1. Figure 3.
Memory organization 2 M95256-W M95256-R M95256-DR M95256-DF Memory organization The memory is organized as shown in the following figure. Figure 4.
M95256-W M95256-R M95256-DR M95256-DF 3 Signal description Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are described next. 3.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device.
Signal description 3.6 M95256-W M95256-R M95256-DR M95256-DF Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all Write instructions. 3.7 VCC supply voltage VCC is the supply voltage. 3.
M95256-W M95256-R M95256-DR M95256-DF 4 Connecting to the SPI bus Connecting to the SPI bus All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first.
Connecting to the SPI bus 4.1 M95256-W M95256-R M95256-DR M95256-DF SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).
M95256-W M95256-R M95256-DR M95256-DF 5 Operating features 5.1 Supply voltage (VCC) 5.1.1 Operating supply voltage VCC Operating features Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 9: DC and AC parameters).
Operating features 5.1.4 M95256-W M95256-R M95256-DR M95256-DF Power-down During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage defined under Operating conditions in Section 9: DC and AC parameters), the device must be: 5.2 ● deselected (Chip Select S should be allowed to follow the voltage applied on VCC), ● in Standby Power mode (there should not be any internal write cycle in progress).
M95256-W M95256-R M95256-DR M95256-DF Operating features The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C) is already low. Figure 7 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. 5.4 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.
Instructions 6 M95256-W M95256-R M95256-DR M95256-DF Instructions Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3.
M95256-W M95256-R M95256-DR M95256-DF 6.1 Instructions Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state.
Instructions 6.2 M95256-W M95256-R M95256-DR M95256-DF Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high.
M95256-W M95256-R M95256-DR M95256-DF 6.3 Instructions Read Status Register (RDSR) The Read Status Register (RDSR) instruction is used to read the Status Register. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10.
Instructions 6.3.4 M95256-W M95256-R M95256-DR M95256-DF SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal enable the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low).
M95256-W M95256-R M95256-DR M95256-DF Instructions Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed Write cycle that takes tW to complete (as specified in AC tables under Section 9: DC and AC parameters). While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle tW, and 0 when the Write cycle is complete.
Instructions M95256-W M95256-R M95256-DR M95256-DF When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two cases should be considered, depending on the state of the Write Protect (W) input pin: ● If Write Protect (W) is driven high, it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction).
M95256-W M95256-R M95256-DR M95256-DF Instructions When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. 6.
Instructions M95256-W M95256-R M95256-DR M95256-DF The instruction is not accepted, and is not executed, under the following conditions: Note: ● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before), ● if a Write cycle is already in progress, ● if the device has not been deselected, by driving high Chip Select (S), at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in), ● if the addressed page is in t
M95256-W M95256-R M95256-DR M95256-DF 6.6.1 Instructions Cycling with Error Correction Code (ECC) M95256 and M95256-D devices offer an Error Correction Code (ECC) logic. The ECC is an internal logic function which is transparent for the SPI communication protocol. The ECC logic is implemented on each group of four EEPROM bytes(c). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value.
Instructions 6.7 M95256-W M95256-R M95256-DR M95256-DF Read Identification Page (available only in M95256-D devices) The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see Table 4). The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D).
M95256-W M95256-R M95256-DR M95256-DF 6.8 Instructions Write Identification Page (available only in M95256-D devices) The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Table 4). The Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on Serial Data Input (D).
Instructions 6.9 M95256-W M95256-R M95256-DR M95256-DF Read Lock Status (available only in M95256-D devices) The Read Lock Status instruction (see Table 4) is used to check whether the Identification Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data Input (D). Address bit A10 must be 1, all other address bits are Don't Care.
M95256-W M95256-R M95256-DR M95256-DF 6.10 Instructions Lock ID (available only in M95256-D devices) The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high.
Power-up and delivery state M95256-W M95256-R M95256-DR M95256-DF 7 Power-up and delivery state 7.1 Power-up state After power-up, the device is in the following state: ● Standby power mode, ● deselected (after power-up, a falling edge is required on Chip Select (S) before any instructions can be started), ● not in the Hold condition, ● the Write Enable Latch (WEL) is reset to 0, ● Write In Progress (WIP) is reset to 0.
M95256-W M95256-R M95256-DR M95256-DF 8 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 8 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8.
DC and AC parameters 9 M95256-W M95256-R M95256-DR M95256-DF DC and AC parameters This section summarizes the operating conditions and the DC/AC characteristics of the device. Table 9. Operating conditions (M95256-W, device grade 6) Symbol VCC TA Table 10. Parameter Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature –40 85 °C Operating conditions (M95256-R and M95256-DR, device grade 6) Symbol VCC TA Table 11. Parameter Min. Max. Unit Supply voltage 1.8 5.
M95256-W M95256-R M95256-DR M95256-DF Table 13. Capacitance Symbol COUT CIN DC and AC parameters Test conditions(1) Parameter Max. Unit VOUT = 0 V 8 pF Input capacitance (D) VIN = 0 V 8 pF Input capacitance (other pins) VIN = 0 V 6 pF Output capacitance (Q) Min. 1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz. Table 14. Symbol Ncycle Cycling performance by groups of four bytes Parameter(1) Test conditions Write cycle endurance(2) Min. Max.
DC and AC parameters Table 16. Symbol M95256-W M95256-R M95256-DR M95256-DF DC characteristics (M95256-W, device grade 6) Parameter Test conditions Min. Max. Unit ILI Input leakage current VIN = VSS or VCC ±2 µA ILO Output leakage current S = VCC, VOUT = VSS or VCC ±2 µA VCC= 2.5 V, C = 0.1 VCC/0.9 VCC at 5 MHz, Q = open 3(1) VCC= 2.5 V, C = 0.1 VCC/0.9 VCC at 10 MHz, Q = open 2(2) VCC= 5.5 V, C = 0.1 VCC/0.9 VCC at 5 MHz, Q = open 5(1) VCC= 5.5 V, C = 0.1 VCC/0.
M95256-W M95256-R M95256-DR M95256-DF Table 17. Symbol DC and AC parameters DC characteristics (M95256-R, M95256-DR, device grade 6) Test conditions(1) Parameter Min. Max. Unit ILI Input leakage current VIN = VSS or VCC ±2 µA ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC ±2 µA VCC = 1.8 V, C = 0.1 VCC or 0.9 VCC, at 2 MHz, Q = open 1(2) VCC = 1.8 V, C = 0.1 VCC or 0.
DC and AC parameters Table 18. Symbol M95256-W M95256-R M95256-DR M95256-DF DC characteristics (M95256-DF, device grade 6) Test conditions(1) Parameter Min. Max. Unit ILI Input leakage current VIN = VSS or VCC ±2 µA ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC ±2 µA ICC Supply current (Read) VCC = 1.7 V, C = 0.1 VCC or 0.9 VCC, at 5 MHz, Q = open 2 mA ICC0(2) Supply current (Write) VCC = 1.
M95256-W M95256-R M95256-DR M95256-DF Table 19. AC characteristics (M95256-W, device grade 6) Test conditions specified in Table 9 and Table 12 Symbol DC and AC parameters Alt. Parameter Previous(1) and new products CL = 100 pF New products(2) CL = 30 pF Vcc ≥ 2.5V Vcc ≥ 4.5V Min. Max. Min. Max. Min. Max. D.C. 5 D.C. 10 D.C.
DC and AC parameters Table 20. M95256-W M95256-R M95256-DR M95256-DF AC characteristics (M95256-R, M95256-DR device grade 6) Test conditions specified in Table 10 and Table 12 New products (2) Previous products Symbol Alt. Vcc ≥ 1.8V (1) Parameter Vcc ≥ 2.5V Vcc ≥ 4.5V Unit Min. Max. Min. Max. Min. Max. Min. Max.
M95256-W M95256-R M95256-DR M95256-DF Table 21. DC and AC parameters AC characteristics (M95256-DF device grade 6) Test conditions specified in Table 10 and Table 12(1) Vcc ≥ 1.7 V Vcc ≥ 2.5 V Vcc ≥ 4.5 V Parameter fSCK fC Unit Min. Max. Min. Max. 5 10 Clock frequency Min. Max.
DC and AC parameters M95256-W M95256-R M95256-DR M95256-DF Figure 20. Serial input timing tSHSL S tCHSL tCH tSLCH tCHSH tSHCH C tDVCH tCHCL tCL tCLCH tCHDX D Q LSB IN MSB IN High impedance AI01447d Figure 21.
M95256-W M95256-R M95256-DR M95256-DF DC and AC parameters Figure 22.
Package mechanical data 10 M95256-W M95256-R M95256-DR M95256-DF Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.
M95256-W M95256-R M95256-DR M95256-DF Package mechanical data Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline E $ , , 0IN % B % + , ! $ EEE ! :7?-%E6 1. Drawing is not to scale. 2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 23.
Package mechanical data M95256-W M95256-R M95256-DR M95256-DF Figure 25. TSSOP8 – 8-lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 24. TSSOP8 – 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ Min A Max 0.050 0.150 0.800 1.050 b 0.190 c 0.090 1.000 CP Max 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.
M95256-W M95256-R M95256-DR M95256-DF Package mechanical data Figure 26. M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline BBB : $ 8 ( 9 2EFERENCE E & E AAA ! ! 8 7AFER BACK SIDE E & $ETAIL ! % E ' /RIENTATION "UMPS SIDE 3IDE VIEW "UMP ! EEE : B CCC DDD : 3EATING PLANE - : 89 - : $ETAIL ! 2OTATED #G?-%?6 1. Drawing is not to scale.
Package mechanical data Table 25. M95256-W M95256-R M95256-DR M95256-DF M95256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.540 0.500 0.580 0.0213 0.0197 0.0228 A1 0.190 0.0075 A2 0.350 0.0138 b 0.270 0.0106 D 1.271 1.291 0.0500 0.0508 E 1.358 1.378 0.0535 0.0543 e 0.800 0.0315 e1 0.693 0.0273 e2 0.400 0.0157 e3 0.400 0.0157 F 0.333 0.0131 G 0.235 0.0093 H 0.236 0.
M95256-W M95256-R M95256-DR M95256-DF 11 Part numbering Part numbering Table 26. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM M95256-D W MN 6 T P /K Device function 256 = 256 Kbit Device family Blank = without Identification page D =With additional Identification page Operating voltage W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.
Revision history 12 Revision history Table 27. 48/53 M95256-W M95256-R M95256-DR M95256-DF Document revision history Date Revision Changes 17-Nov-1999 2.1 New -V voltage range added (including the tables for DC characteristics, AC characteristics, and ordering information). 07-Feb-2000 2.2 New -V voltage range extended to M95256 (including AC characteristics, and ordering information). 22-Feb-2000 2.3 tCLCH and tCHCL, for the M95xxx-V, changed from 1μs to 100ns 15-Mar-2000 2.
M95256-W M95256-R M95256-DR M95256-DF Table 27. Date Revision history Document revision history (continued) Revision Changes 6 M95128 part numbers removed from document. PDIP8 package removed. Delivery state paragraph added. Section 3.8: Operating supply voltage (VCC) added and information removed below Section 4: Operating features. Power up state removed below Section 6: Delivery state. Figure 18: SPI modes supported modified and Note 2 added. Note 1 added to Table 8.
Revision history Table 27. Date 24-Jun-2010 07-Sep-2010 12-Nov-2010 M95256-W M95256-R M95256-DR M95256-DF Document revision history (continued) Revision Changes 10 M95080 part number added. Updated Section 3.8: Operating supply voltage (VCC) Updated Section 4.3: Data protection and protocol control Updated Section 5.4: Write Status Register (WRSR) Added note in Section 5.
M95256-W M95256-R M95256-DR M95256-DF Table 27. Date 22-Mar-2011 Revision history Document revision history (continued) Revision 13 Changes (...
Revision history Table 27. Date 21-Jun-2012 24-Jul-2012 52/53 M95256-W M95256-R M95256-DR M95256-DF Document revision history (continued) Revision Changes 18 Datasheet split into: – M95256-125 datasheet for automotive products (range 3), – M95256-W, M95256-R, M95256-DR, M95256-DF (this datasheet) for standard products (range 6). Added: – 1.
M95256-W M95256-R M95256-DR M95256-DF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.
