Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller DIL-20

Rev. 3.2

July 2001 1/100

ST6200C/ST6201C/ST6203C

8-BIT MCUs WITH A/D CONVERTER,

TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET

■ Memories

– 1K or 2K bytes Program memory (OTP,

EPROM, FASTROM or ROM) with read-out

protection

– 64 bytes RAM

■ Clock, Reset and Supply Management

– Enhanced reset system

– Low Voltage Detector (LVD) for Safe Reset

– Clock sources: crystal/ceramic resonator or

RC network, external clock, backup oscillator

(LFAO)

– Oscillator Safeguard (OSG)

– 2 Power Saving Modes: Wait and Stop

■ Interrupt Management

– 4 interrupt vectors plus NMI and RESET

– 9 external interrupt lines (on 2 vectors)

■ 9 I/O Ports

– 9 multifunctional bidirectional I/O lines

– 4 alternate function lines

– 3 high sink outputs (20mA)

■ 2 Timers

– Configurable watchdog timer

– 8-bit timer/counter with a 7-bit prescaler

■ Analog Peripheral

– 8-bit ADC with 4 input channels (except on

ST6203C)

■ Instruction Set

– 8-bit data manipulation

– 40 basic instructions

– 9 addressing modes

– Bit manipulation

■ Development Tools

– Full hardware/software development package

Device Summary

(See Section 11.5 for Ordering Information)

PDIP16

SO16

CDIP16W

SSOP16

Features

ST62T00C(OTP)

ST6200C(ROM)

ST62P00C(FASTROM)

ST62T01C(OTP)

ST6201C(ROM)

ST62P01C(FASTROM)

ST62T03C(OTP)

ST6203C(ROM)

ST62P03C(FASTROM)

ST62E01C(EPROM)

Program memory - bytes 1K 2K 1K 2K

RAM - bytes 64

Operating Supply 3.0V to 6V

Analog Inputs 4 - 4

Clock Frequency 8MHz Max

Operating Temperature -40°C to +125°C

Packages PDIP16 / SO16 / SSOP16 CDIP16W

Summary of content (101 pages)

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ST6200C/ST6201C/ST6203C 8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET ■ ■ ■ ■ ■ ■ ■ Memories – 1K or 2K bytes Program memory (OTP, EPROM, FASTROM or ROM) with read-out protection – 64 bytes RAM Clock, Reset and Supply Management – Enhanced reset system – Low Voltage Detector (LVD) for Safe Reset – Clock sources: crystal/ceramic resonator or RC network, external clock, backup oscillator (LFAO) – Oscillator Safeguard (OSG) – 2 Power Saving Modes: Wait and Stop Interrupt M
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Table of Contents ST6200C/ST6201C/ST6203C . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . 8 3.1 MEMORY AND REGISTER MAPS . . . .
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Table of Contents 6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 10.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.
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ST6200C/ST6201C/ST6203C 1 INTRODUCTION The ST6200C, 01C and 03C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip peripherals.
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ST6200C/ST6201C/ST6203C 2 PIN DESCRIPTION Figure 2. 16-Pin Package Pinout VDD 1 16 VSS OSCin 2 15 PA1/20mA Sink it1 OSCout 3 14 PA2/20mA Sink NMI VPP RESET 4 13 PA3/20mA Sink 5 12 6 11 PB0 PB1 Ain*/PB7 Ain*/PB6 7 8 it2 10 it2 9 PB3/Ain* PB5/Ain* itX associated interrupt vector * Depending on device. Please refer to I/O Port section. Pin n° Pin Name Type Table 1.
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ST6200C/ST6201C/ST6203C 3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES 3.1 MEMORY AND REGISTER MAPS 3.1.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs.
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ST6200C/ST6201C/ST6203C MEMORY MAP (Cont’d) Figure 4.
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ST6200C/ST6201C/ST6203C MEMORY MAP (Cont’d) 3.1.2 Program Space Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register). Thus, the MCU is capable of addressing 4K bytes of memory directly. 3.1.
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ST6200C/ST6201C/ST6203C MEMORY MAP (Cont’d) Table 2.
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ST6200C/ST6201C/ST6203C MEMORY MAP (Cont’d) 3.1.6 Data ROM Window The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh. There are 64 blocks of 64 bytes in a 4K device: – Block 0 is related to the address range 0000h to 003Fh. – Block 1 is related to the address range 0040h to 007Fh. and so on...
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ST6200C/ST6201C/ST6203C MEMORY MAP (Cont’d) 3.1.6.2 Data ROM Window memory addressing In cases where some data (look-up tables for example) are stored in program memory, reading these data requires the use of the Data ROM window mechanism. To do this: 1. The DRWR register has to be loaded with the 64-byte block number where the data are located (in program memory). This number also gives the start address of the block. 2.
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ST6200C/ST6201C/ST6203C 3.2 PROGRAMMING MODES 3.2.1 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V PP pin. The programming flow of the ST62T00C, T01/E01C and T03C is described in the User Manual of the EPROM Programming Board. Table 3.
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ST6200C/ST6201C/ST6203C 3.3 OPTION BYTES Each device is available for production in user programmable versions (OTP) as well as in factory coded versions (ROM). OTP devices are shipped to customers with a default content (00h), while ROM factory coded parts contain the code supplied by the customer. This implies that OTP devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured.
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ST6200C/ST6201C/ST6203C 4 CENTRAL PROCESSING UNIT 4.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. 4.
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ST6200C/ST6201C/ST6203C CPU REGISTERS (Cont’d) The 12-bit length allows the direct addressing of 4096 bytes in Program Space. However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program ROM Page register. The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC.
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ST6200C/ST6201C/ST6203C 5 CLOCKS, SUPPLY AND RESET 5.1 CLOCK SYSTEM The main oscillator of the MCU can be driven by any of these clock sources: – external clock signal – external AT-cut parallel-resonant crystal – external ceramic resonator – external RC network (RNET). In addition, an on-chip Low Frequency Auxiliary Oscillator (LFAO) is available as a back-up clock system or to reduce power consumption.
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ST6200C/ST6201C/ST6203C Table 5. Oscillator Configurations Crystal/Resonator Option1) Crystal/Resonator Option1) Hardware Configuration External Clock ST6 OSCin OSCout NC EXTERNAL CLOCK Crystal/Resonator Clock 2) ST6 OSCin CL1 OSCout LOAD CAPACITORS 3) CL2 RC Network Option1) RC Network OSG Enabled Option1) CLOCK SYSTEM (Cont’d) 5.1.
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ST6200C/ST6201C/ST6203C CLOCK SYSTEM (Cont’d) 5.1.2 Oscillator Safeguard (OSG) The Oscillator Safeguard (OSG) feature is a means of dramatically improving the operational integrity of the MCU. It is available when the OSG ENABLED option is selected in the option byte (refer to the Option Bytes section of this document).
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ST6200C/ST6201C/ST6203C CLOCK SYSTEM (Cont’d) 5.1.3 Low Frequency Auxiliary Oscillator (LFAO) The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as a backup oscillator in case of main oscillator failure.
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ST6200C/ST6201C/ST6203C 5.2 LOW VOLTAGE DETECTOR (LVD) The on-chip Low Voltage Detector is enabled by setting a bit in the option bytes (refer to the Option Bytes section of this document). The LVD allows the device to be used without any external RESET circuitry. In this case, the RESET pin should be left unconnected. If the LVD is not used, an external circuit is mandatory to ensure correct Power On Reset operation, see figure in the Reset section.
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ST6200C/ST6201C/ST6203C 5.3 RESET 5.3.1 Introduction The MCU can be reset in three ways: ■ A low pulse input on the RESET pin ■ Internal Watchdog reset ■ Internal Low Voltage Detector (LVD) reset 5.3.
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ST6200C/ST6201C/ST6203C RESET (Cont’d) 5.3.3 RESET Pin The RESET pin may be connected to a device on the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the internal state of the MCU and ensure it starts-up correctly. The pin, which is connected to an internal pull-up, is active low and features a Schmitt trigger input.
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ST6200C/ST6201C/ST6203C RESET (Cont’d) 5.3.4 Watchdog Reset The MCU provides a Watchdog timer function in order to be able to recover from software hangups. If the Watchdog register is not refreshed before an end-of-count condition is reached, a Watchdog reset is generated. After a Watchdog reset, the MCU restarts in the same way as if a Reset was generated by the RESET pin. Note: When a watchdog reset occurs, the RESET pin is tied low for very short time period, to flag the reset phase.
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ST6200C/ST6201C/ST6203C 5.4 INTERRUPTS The ST6 core may be interrupted by four maskable interrupt sources, in addition to a Non Maskable Interrupt (NMI) source. The interrupt processing flowchart is shown in Figure 18. Maskable interrupts must be enabled by setting the GEN bit in the IOR register. However, even if they are disabled (GEN bit = 0), interrupt events are latched and may be processed as soon as the GEN bit is set.
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ST6200C/ST6201C/ST6203C 5.5 INTERRUPT MANAGEMENT ■ ■ ■ RULES AND PRIORITY A Reset can interrupt the NMI and peripheral interrupt routines The Non Maskable Interrupt request has the highest priority and can interrupt any peripheral interrupt routine at any time but cannot interrupt another NMI interrupt. No peripheral interrupt can interrupt another.
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ST6200C/ST6201C/ST6203C 5.9 EXTERNAL INTERRUPTS (I/O Ports) External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the GEN bit is set. These interrupts allow the processor to exit from STOP mode. The external interrupt polarity is selected through the IOR register. External interrupts are linked to vectors #1 and # 2. Interrupt requests on vector #1 can be configured either as edge or level-sensitive using the LES bit in the IOR Register.
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ST6200C/ST6201C/ST6203C 5.10 INTERRUPT HANDLING PROCEDURE The interrupt procedure is very similar to a call procedure, in fact the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred. As a result, the user should save all Data space registers which may be used within the interrupt routines.
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ST6200C/ST6201C/ST6203C 5.11 REGISTER DESCRIPTION INTERRUPT OPTION REGISTER (IOR) Address: 0C8h — Write Only Reset status: 00h 7 - 1: Low level sensitive mode is selected for interrupt vector #1 0 LES ESB GEN - - - - Caution: This register is write-only and cannot be accessed by single-bit operations (SET, RES, DEC,...). Bit 7 =Reserved, must be cleared. Bit 6 = LES Level/Edge Selection bit. 0: Falling edge sensitive mode is selected for interrupt vector #1 Bit 5 = ESB Edge Selection bit.
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ST6200C/ST6201C/ST6203C 6 POWER SAVING MODES 6.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST6 (see Figure 19). In addition, the Low Frequency Auxiliary Oscillator (LFAO) can be used instead of the main oscillator to reduce power consumption in RUN and WAIT modes. After a RESET the normal operating mode is selected by default (RUN mode).
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ST6200C/ST6201C/ST6203C 6.2 WAIT MODE The MCU goes into WAIT mode as soon as the WAIT instruction is executed. This has the following effects: – Program execution is stopped, the microcontroller software can be considered as being in a “frozen” state. – RAM contents and peripheral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage. – The oscillator is kept running to provide a clock to the peripherals; they are still active.
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ST6200C/ST6201C/ST6203C 6.3 STOP MODE STOP mode is the lowest power consumption mode of the MCU (see Figure 22). The MCU goes into STOP mode as soon as the STOP instruction is executed. This has the following effects: – Program execution is stopped, the microcontroller can be considered as being “frozen”. – The contents of RAM and the peripheral registers are kept safely as long as the power supply voltage is higher than the RAM retention voltage.
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ST6200C/ST6201C/ST6203C STOP MODE (Cont’d) Figure 22.
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ST6200C/ST6201C/ST6203C 6.4 NOTES RELATED TO WAIT AND STOP MODES 6.4.1 Exit from Wait and Stop Modes 6.4.1.1 NMI Interrupt It should be noted that when the GEN bit in the IOR register is low (interrupts disabled), the NMI interrupt is active but cannot cause a wake up from STOP/WAIT modes. 6.4.1.
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ST6200C/ST6201C/ST6203C 7 I/O PORTS 7.1 INTRODUCTION Each I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without pull-up and interrupt generation), digital output (open drain, push-pull) or analog input (when available). The I/O pins can be used in either standard or alternate function mode.
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ST6200C/ST6201C/ST6203C I/O PORTS (Cont’d) Figure 23. I/O Port Block Diagram PULL-UP RESET VDD VDD DATA DIRECTION REGISTER VDD Pxx I/O Pin DATA REGISTER ST6 INTERNAL BUS N-BUFFER OPTION REGISTER P-BUFFER CLAMPING DIODES CMOS SCHMITT TO INTERRUPT TO ADC TRIGGER * * Depending on device. See device summary on page 1. Table 8.
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ST6200C/ST6201C/ST6203C I/O PORTS (Cont’d) 7.2.5 Instructions NOT to be used to access Port Data registers (SET, RES, INC and DEC) DO NOT USE READ-MODIFY-WRITE INSTRUCTIONS (SET, RES, INC and DEC) ON PORT DATA REGISTERS IF ANY PIN OF THE PORT IS CONFIGURED IN INPUT MODE. These instructions make an implicit read and write back of the entire register. In port input mode, however, the data register reads from the input pins directly, and not from the data register latches.
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ST6200C/ST6201C/ST6203C I/O PORTS (Cont’d) Table 9.
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ST6200C/ST6201C/ST6203C I/O PORTS (Cont’d) Bit 7:0 = DD[7:0] Data direction register bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode 7.5 REGISTER DESCRIPTION DATA REGISTER (DR) Port x Data Register DRx with x = A or B. Address DRA: 0C0h - Read /Write Address DRB: 0C1h - Read /Write OPTION REGISTER (OR) Port x Option Register ORx with x = A or B.
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ST6200C/ST6201C/ST6203C 8 ON-CHIP PERIPHERALS 8.1 WATCHDOG TIMER (WDG) 8.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the SR bit becomes cleared. 8.1.
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ST6200C/ST6201C/ST6203C WATCHDOG TIMER (Cont’d) 8.1.3 Functional Description The watchdog activation is selected through an option in the option bytes: – HARDWARE Watchdog option After reset, the watchdog is permanently active, the C bit in the WDGR is forced high and the user can not change it. However, this bit can be read equally as 0 or 1. – SOFTWARE Watchdog option After reset, the watchdog is deactivated. The function is activated by setting C bit in the WDGR register.
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ST6200C/ST6201C/ST6203C WATCHDOG TIMER (Cont’d) These instructions test the C bit and reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. For more information on the use of the watchdog, please read application note AN1015. Note: This note applies only when the watchdog is used as a standard timer.
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ST6200C/ST6201C/ST6203C WATCHDOG TIMER (Cont’d) 8.1.7 Register Description WATCHDOG REGISTER (WDGR) Address: 0D8h - Read /Write Reset Value: 1111 1110 (FE h) 7 T0 0 T1 T2 T3 T4 T5 SR C Bits 7:2 = T[5:0] Downcounter bits Caution: These bits are reversed and shifted with respect to the physical counter: bit-7 (T0) is the LSB of the Watchdog downcounter and bit-2 (T5) is the MSB. Bit 1 = SR: Software Reset bit Software can generate a reset by clearing this bit while the C bit is set.
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ST6200C/ST6201C/ST6203C 8.2 8-BIT TIMER 8.2.1 Introduction The 8-Bit Timer on-chip peripheral is a free running downcounter based on an 8-bit downcounter with a 7-bit programmable prescaler, giving a maximum count of 215. 8.2.2 Main Features ■ Time-out downcounting mode with up to 15-bit accuracy ■ Interrupt capability on counter underflow The timer can be used in WAIT mode to wake up the MCU. Figure 27.
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ST6200C/ST6201C/ST6203C 8-BIT TIMER (Cont’d) 8.2.3 Counter/Prescaler Description Prescaler The prescaler input is the internal frequency f INT divided by 12. The prescaler decrements on the rising edge, depending on the division factor programmed by the PS[2:0] bits in the TSCR register. The state of the 7-bit prescaler can be read in the PSCR register. When the prescaler reaches 0, it is automatically reloaded with 7Fh.
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ST6200C/ST6201C/ST6203C 8-BIT TIMER (Cont’d) 8.2.6 Register Description PRESCALER COUNTER REGISTER (PSCR) Address: 0D2h - Read/Write Reset Value: 0111 1111 (7Fh) 7 0 Bit 6 = ETI Enable Timer Interrupt. When set, enables the timer interrupt request. If ETI=0 the timer interrupt is disabled. If ETI=1 and TMZ=1 an interrupt request is generated. 0: Interrupt disabled (reset state) 1: Interrupt enabled PSCR PSCR PSCR PSCR PSCR PSCR PSCR PSCR 7 6 5 4 3 2 1 0 Bit 5 = TSCR5 Reserved, must be set.
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ST6200C/ST6201C/ST6203C 8.3 A/D CONVERTER (ADC) 8.3.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control Register. 8.3.
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ST6200C/ST6201C/ST6203C A/D CONVERTER (Cont’d) 8.3.3 Functional Description 8.3.3.1 Analog Power Supply The high and low level reference voltage pins are internally connected to the V DD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. 8.3.3.
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ST6200C/ST6201C/ST6203C A/D CONVERTER (Cont’d) 8.3.4 Recommendations The following six notes provide additional information on using the A/D converter. 1.The A/D converter does not feature a sample and hold circuit. The analog voltage to be measured should therefore be stable during the entire conversion cycle. Voltage variation should not exceed ±1/2 LSB for optimum conversion accuracy. A low pass filter may be used at the analog input pins to reduce input voltage variation during conversion. 2.
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ST6200C/ST6201C/ST6203C A/D CONVERTER (Cont’d) 8.3.5 Low Power Modes Mode cally cleared when the STA bit is set. Data in the data conversion register are valid only when this bit is set to “1”. 0: Conversion is not complete 1: Conversion can be read from the ADR register Description No effect on A/D Converter. ADC interrupts cause the device to exit from Wait mode. A/D Converter disabled. WAIT STOP Note: The A/D converter may be disabled by clearing the PDS bit.
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ST6200C/ST6201C/ST6203C 9 INSTRUCTION SET 9.1 ST6 ARCHITECTURE The ST6 architecture has been designed for maximum efficiency while keeping byte usage to a minimum; in short, to provide byte-efficient programming. The ST6 core has the ability to set or clear any register or RAM location bit in Data space using a single instruction. Furthermore, programs can branch to a selected address depending on the status of any bit in Data space. 9.
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ST6200C/ST6201C/ST6203C 9.3 INSTRUCTION SET The ST6 offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be divided into six different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following paragraphs describe the different types. All the instructions belonging to a given type are presented in individual tables. Load & Store.
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ST6200C/ST6201C/ST6203C INSTRUCTION SET (Cont’d) either a data space memory location or an immediate value. In CLR, DEC, INC instructions the operand can be any of the 256 data space addresses. In COM, RLC, SLA the operand is always the accumulator. Arithmetic and Logic. These instructions are used to perform arithmetic calculations and logic operations. In AND, ADD, CP, SUB instructions one operand is always the accumulator while, depending on the addressing mode, the other can be Table 16.
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ST6200C/ST6201C/ST6203C INSTRUCTION SET (Cont’d) Conditional Branch. Branch instructions perform a branch in the program when the selected condition is met. Control Instructions. Control instructions control microcontroller operations during program execution. Bit Manipulation Instructions. These instructions can handle any bit in Data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations. Jump and Call.
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ST6200C/ST6201C/ST6203C Opcode Map Summary.
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ST6200C/ST6201C/ST6203C Opcode Map Summary (Continued) LOW 8 1000 HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr 9 1001 4 A 1010 JP 2 abc 2 4 ext 1 JP 2 abc 2 4 ext 1 JP 2 abc 2 4 ext 1 JP 2
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ST6200C/ST6201C/ST6203C 10 ELECTRICAL CHARACTERISTICS 10.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to V SS. 10.1.1 Minimum and Maximum Values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25°C and TA=TAmax (given by the selected temperature range).
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ST6200C/ST6201C/ST6203C 10.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi10.2.1 Voltage Characteristics Symbol VDD - VSS VIN VOUT VESD(HBM) tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Ratings Maximum value Supply voltage Unit 7 Input voltage on any pin 1) & 2) VSS-0.
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ST6200C/ST6201C/ST6203C 10.3 OPERATING CONDITIONS 10.3.1 General Operating Conditions Symbol Parameter VDD Conditions Supply voltage fOSC Oscillator frequency VDD Operating Supply Voltage Ambient temperature range TA Min Max Unit V see Figure 32 3.0 6 VDD=3.0V, 1 & 6 Suffix 0 1) 4 VDD=3.0V, 3 Suffix 0 1) 4 VDD=3.6V, 1 & 6Suffix 0 1) 8 VDD=3.6V, 3 Suffix 0 1) 4 fOSC=4MHz, 1 & 6 Suffix 3.0 6.0 fOSC=4MHz, 3 Suffix 3.0 6.0 fOSC=8MHz, 1 & 6 Suffix 3.6 6.
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ST6200C/ST6201C/ST6203C OPERATING CONDITIONS (Cont’d) 10.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V DD, fOSC, and TA. Min Typ 1) Max VIT+ Reset release threshold (VDD rise) 3.9 4.1 4.3 VIT- Reset generation threshold (VDD fall) 3.6 3.
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ST6200C/ST6201C/ST6203C 10.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST6 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total de10.4.1 RUN Modes Parameter Typ 1) Max 2) fOSC=32kHz fOSC=1MHz fOSC=2MHz fOSC=4MHz fOSC=8MHz 0.5 1.3 1.6 2.2 3.3 0.7 1.7 2.4 3.3 4.8 fOSC=32kHz fOSC=1MHz fOSC=2MHz fOSC=4MHz fOSC=8MHz 0.3 0.6 0.9 1.0 1.8 0.4 0.8 1.2 1.5 2.
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ST6200C/ST6201C/ST6203C SUPPLY CURRENT CHARACTERISTICS (Cont’d) 10.4.
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ST6200C/ST6201C/ST6203C SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 38. Typical IDD in WAIT vs fCPU and Temperature for OTP devices with option bytes not programmed IDD [µA] IDD [µA] 800 700 700 8MHz 1M 4MHz 32KHz 2MHz 8MHz 1MHz 4MHz 32KHz 2MHz 600 600 500 500 400 400 300 200 300 100 0 200 3 4 5 6 -40 VDD [V] 25 95 125 T[°C] Figure 39.
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ST6200C/ST6201C/ST6203C SUPPLY CURRENT CHARACTERISTICS (Cont’d) Figure 40.
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ST6200C/ST6201C/ST6203C SUPPLY CURRENT CHARACTERISTICS (Cont’d) 10.4.3 STOP Mode Symbol Parameter Supply current in STOP mode 2) (see Figure 41 & Figure 42) IDD Typ 1) Conditions OTP devices 0.3 ROM devices 0.1 Max Unit 10 3) 20 4) 2 3) 20 4) µA Notes: 1. Typical data are based on VDD=5.0V at TA=25°C. 2. All I/O pins in input with pull-up mode (no load), all peripherals in reset state, OSG and LVD disabled, option bytes programmed to 00H.
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ST6200C/ST6201C/ST6203C SUPPLY CURRENT CHARACTERISTICS (Cont’d) 10.4.4 Supply and Clock System The previous current consumption specified for the ST6 functional operating modes over temperature range does not take into account the clock Symbol source current consumption. To get the total device consumption, the two current values must be added (except for STOP mode). Parameter Typ 1) Conditions Supply current of RC oscillator IDD(CK) fOSC=32 kHz, fOSC=1 MHz fOSC=2 MHz fOSC=4 MHz fOSC=8 MHz VDD=5.
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ST6200C/ST6201C/ST6203C 10.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V DD, fOSC, and TA. 10.5.1 General Timings Symbol tc(INST) tv(IT) Parameter Instruction cycle time Interrupt reaction time tv(IT) = ∆tc(INST) + 6 Conditions fCPU=8 MHz 2) fCPU=8 MHz Min Typ 1) Max Unit 2 4 5 tCPU 3.25 6.5 8.125 µs 6 11 tCPU 9.75 17.875 µs Max Unit 10.5.
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ST6200C/ST6201C/ST6203C CLOCK AND TIMING CHARACTERISTICS (Cont’d) 10.5.3 Crystal and Ceramic Resonator Oscillators The ST6 internal clock can be supplied with several different Crystal/Ceramic resonator oscillators. Only parallel resonant crystals can be used. All the information given in this paragraph are based on Symbol characterization results with specified typical external components. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).
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ST6200C/ST6201C/ST6203C CLOCK AND TIMING CHARACTERISTICS (Cont’d) 10.5.4 RC Oscillator The ST6 internal clock can be supplied with an external RC oscillator. Depending on the RNET value, the accuracy of the frequency is about 20%, so it may not be suitable for some applications. fOSC RNET Parameter Conditions 3V≤VDD≤3.6V 4.5V≤VDD≤6.0V Symbol RC oscillator frequency 1) RC Oscillator external resistor 2) Min Typ Max RNET=22 kΩ RNET=47 kΩ RNET=100 kΩ RNET=220 kΩ RNET=470 kΩ 7.2 5.1 3.2 1.8 0.9 8.
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ST6200C/ST6201C/ST6203C CLOCK AND TIMING CHARACTERISTICS (Cont’d) Figure 46. Typical RC Oscillator frequency vs. VDD fosc [MHz] Rnet=22KOhm 12 Rnet=47KOhm fosc [MHz] Rnet=220KOhm 8 Rnet=22KOhm Rnet=47KOhm 10 Rnet=100KOhm 10 Figure 47. Typical RC Oscillator frequency vs. Temperature (VDD = 5V) Rnet=100KOhm Rnet=220KOhm 8 Rnet=470KOhm 6 6 4 4 2 2 0 Rnet=470KOhm 0 3 4 5 6 -40 25 VDD [V] 95 125 Ta [°C] 10.5.
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ST6200C/ST6201C/ST6203C 10.6 MEMORY CHARACTERISTICS Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. 10.6.1 RAM and Hardware Registers Symbol Parameter Conditions Min Data retention1) VRM Typ Max 0.7 Unit V 10.6.2 EPROM Program Memory Symbol tret Parameter Data Conditions retention 2) TA=+55°C Min 3) Typ Max 10 Unit years Figure 49. EPROM Retention Time vs. Temperature Retention time [Years] 100000 10000 1000 100 10 1 0.
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ST6200C/ST6201C/ST6203C 10.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 10.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).
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ST6200C/ST6201C/ST6203C EMC CHARACTERISTICS (Cont’d) 10.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the AN1181 application note. 10.7.2.
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ST6200C/ST6201C/ST6203C EMC CHARACTERISTICS (Cont’d) 10.7.2.2 Static and Dynamic Latch-Up ■ LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample. This test conforms to the EIA/ JESD 78 IC latch-up standard. For more details, refer to the AN1181 application note.
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ST6200C/ST6201C/ST6203C EMC CHARACTERISTICS (Cont’d) 10.7.3 ESD Pin Protection Strategy To protect an integrated circuit against ElectroStatic Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress.
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ST6200C/ST6201C/ST6203C 10.8 I/O PORT PIN CHARACTERISTICS 10.8.1 General Characteristics Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. Symbol Parameter Conditions Typ 1) 2) VIL Input low level voltage VIH Input high level voltage 2) Vhys VDD=5V Schmitt trigger voltage hysteresis 3) VDD=3.3V Max 0.3xVDD 0.
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ST6200C/ST6201C/ST6203C I/O PORT PIN CHARACTERISTICS (Cont’d) 10.8.2 Output Driving Current Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. Symbol Parameter Conditions Min Max IIO=+10µA, TA≤125°C VOL 1) Output low level voltage for a high sink I/O pin (see Figure 58 and Figure 61) VDD=5V Output low level voltage for a standard I/O pin (see Figure 57 and Figure 60) IIO=+3mA, TA≤125°C 0.8 IIO=+5mA, TA≤85°C 0.8 IIO=+10mA, TA≤85°C 1.
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ST6200C/ST6201C/ST6203C I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 59. Typical VOH at VDD = 5V Voh [V] at Vdd=5V 5 4.5 4 Ta=-40°C Ta=95°C Ta=25°C Ta=125°C 3.5 -8 -6 -4 -2 0 Iio [mA] Figure 60. Typical VOL vs VDD (standard I/Os) Vol [mV] at Iio=2mA Ta=-40°C Ta=95°C Vol [mV] at Iio=5mA 350 Ta=25°C Ta=-40°C Ta=95°C Ta=25°C Ta=125°C 700 Ta=125°C 300 600 250 500 200 400 150 300 3 4 5 6 3 4 VDD [V] 5 6 VDD [V] Figure 61.
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ST6200C/ST6201C/ST6203C I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 62.
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ST6200C/ST6201C/ST6203C 10.9 CONTROL PIN CHARACTERISTICS 10.9.1 Asynchronous RESET Pin Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. Symbol Parameter Conditions Typ 1) Min 2) VIL Input low level voltage VIH Input high level voltage 2) Vhys Schmitt trigger voltage hysteresis 3) Max 0.3xVDD 0.
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ST6200C/ST6201C/ST6203C CONTROL PIN CHARACTERISTICS (Cont’d) VDD O VDD 0.1µF RPU 4.7kΩ f INT STOP MODE RESET EXTERNAL RESET CIRCUIT 7) RESD 1) 0.1µF COUNTER PT IO VDD 2048 external clock cycles NA L Figure 64. Typical Application with RESET pin 8) INTERNAL RESET WATCHDOG RESET LVD RESET 10.9.2 NMI Pin Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
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ST6200C/ST6201C/ST6203C CONTROL PIN CHARACTERISTICS (Cont’d) 10.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (TIMER). 10.10.1 Watchdog Timer Symbol tw(WDG) Parameter Watchdog time-out duration Conditions Min Typ Max Unit 3,072 196,608 tINT fCPU=4MHz 0.768 49.152 ms fCPU=8MHz 0.384 24.
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ST6200C/ST6201C/ST6203C 10.11 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. Symbol fOSC VAIN RAIN Parameter Clock frequency Conversion range voltage Total convertion time tSTAB Stabilization time 4) ACIN 2) Typ 1) Max Unit 1.2 fOSC MHz VSS VDD V Min External input resistor tADC ADI Conditions 10 fOSC=8MHz fOSC=4MHz 3) 70 140 fOSC=8MHz µs 2 4 tCPU 3.25 6.5 µs 1.
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ST6200C/ST6201C/ST6203C 8-BIT ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol Parameter Conditions |ET| Total unadjusted error 1) EO Offset error 1) Gain Error |ED| Differential linearity error 1) Integral linearity error Typ. Max 1.2 ±2, fosc>1.2MHz ±4, fosc>32KHz Unit 0.72 VDD=5V 2) fOSC=8MHz 1) EG |EL| Min -0.31 LSB 0.54 1) Notes: 1. Negative injection disturbs the analog performance of the device.
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ST6200C/ST6201C/ST6203C 11 GENERAL INFORMATION 11.1 PACKAGE MECHANICAL DATA Figure 68. 16-Pin Plastic Dual In-Line Package, 300-mil Width Dim. E mm Min Typ A A2 A A1 L b2 D1 b Min Typ 5.33 Max 0.210 A1 0.38 0.015 A2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 E1 b2 1.14 1.52 1.78 0.045 0.060 0.070 eB b3 0.76 0.99 1.14 0.030 0.039 0.045 0.25 0.36 0.008 0.010 0.014 c e b3 inches Max D c 0.20 D 18.67 19.18 19.69 0.735 0.755 0.775 D1 0.13 e 0.
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ST6200C/ST6201C/ST6203C PACKAGE MECHANICAL DATA (Cont’d) Figure 70. 16-Pin Ceramic Side-Brazed Dual In-Line Package Dim. mm Min Typ A Min Typ 3.78 Max 0.149 A1 0.38 B 0.36 0.46 0.56 0.014 0.018 0.022 B1 0.015 1.14 1.37 1.78 0.045 0.054 0.070 C 0.20 0.25 0.36 0.008 0.010 0.014 D 19.86 20.32 20.78 0.782 0.800 0.818 D1 E1 17.78 0.700 7.04 7.49 7.95 0.277 0.295 0.313 e 2.54 0.100 G 6.35 6.60 6.86 0.250 0.260 0.270 G1 9.47 9.73 9.98 0.373 0.383 0.393 G2 L CDIP16W inches Max 1.
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ST6200C/ST6201C/ST6203C 11.2 THERMAL CHARACTERISTICS Symbol RthJA PD TJmax Ratings Package thermal resistance (junction to ambient) DIP16 SO16 SSOP16 Value 90 90 125 Unit °C/W Power dissipation 1) 500 mW Maximum junction temperature 2) 150 °C Notes: 1. The power dissipation is obtained from the formula PD = PINT + PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation determined by the user. 2.
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ST6200C/ST6201C/ST6203C 11.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines in Figure 72 and Figure 73. Recommended glue for SMD plastic packages: ■ Heraeus: PD945, PD955 ■ Loctite: 3615, 3298 Figure 72. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 5 sec 200 150 SOLDERING PHASE 80°C Temp. [°C] 100 50 COOLING PHASE (ROOM TEMPERATURE) PREHEATING PHASE Time [sec] 0 20 40 60 80 100 120 140 160 Figure 73.
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ST6200C/ST6201C/ST6203C 11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL Table 21. Suggested List of DIP16 Socket Types Package / Probe DIP16 Adaptor / Socket Reference TEXTOOL 216-33-40 Same Footprint X Socket Type Textool Table 22. Suggested List of SO16 Socket Types Package / Probe SO16 Adaptor / Socket Reference Same Footprint Socket Type ENPLAS OTS-16-1.27-04 Open Top YAMAICHI IC51-347.
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ST6200C/ST6201C/ST6203C 11.5 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to STMicroelectronics and also details the ST6 factory coded device type. Figure 74.
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ST6200C/ST6201C/ST6203C 11.6 TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents and the list of the selected FASTROM options. The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly filled OPTION LIST appended. See page 94.
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ST6200C/ST6201C/ST6203C TRANSFER OF CUSTOMER CODE (Cont’d) 11.6.2 ROM VERSION The ST6200C, 01C and 03C are mask programmed ROM version of ST62T00C, T01 and T03C OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. ROM Readout Protection. If the ROM READOUT PROTECTION option is selected, a protection fuse can be blown to prevent any access to the program memory content.
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ST6200C/ST6201C/ST6203C TRANSFER OF CUSTOMER CODE (Cont’d) ST6200C/01C/03C/P00C/P01C/P03C MICROCONTROLLER OPTION LIST Customer: Address: Contact: Phone: Reference: .... .... .... .... .... .... ..... ..... ..... ..... ..... ..... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... ..... ..... ..... ..... ..... ..... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... ....
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ST6200C/ST6201C/ST6203C 12 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST6 microcontroller family. Full details of tools available for the ST6 from third party manufacturers can be ob- tain from the STMicroelectronics Internet site: ➟ http://mcu.st.com. Table 24.
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ST6200C/ST6201C/ST6203C DEVELOPMENT TOOLS (Cont’d) STMicroelectronics Tools Four types of development tool are offered by ST, all of them connect to a PC via a parallel or serial port: see Table 25 and Table 26 for more details. Table 25.
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ST6200C/ST6201C/ST6203C 13 ST6 APPLICATION NOTES IDENTIFICATION DESCRIPTION MOTOR CONTROL AN392 MICROCONTROLLER AND TRIACS ON THE 110/240V MAINS AN414 CONTROLLING A BRUSH DC MOTOR WITH AN ST6265 MCU AN416 SENSORLESS MOTOR DRIVE WITH THE ST62 MCU + TRIAC AN422 IMPROVES UNIVERSAL MOTOR DRIVE AN863 IMPROVED SENSORLESS CONTROL WITH THE ST62 MCU FOR UNIVERSAL MOTOR BATTERY MANAGEMENT AN417 FROM NICD TO NIMH FAST BATTERY CHARGING AN433 ULTRA FAST BATTERY CHARGER USING ST6210 MICROCONTROLLER AN859
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ST6200C/ST6201C/ST6203C IDENTIFICATION DESCRIPTION AN913 PWM GENERATION WITH ST62 16-BIT AUTO-RELOAD TIMER AN914 USING ST626X SPI AS UART AN1016 ST6 USING THE ST623XB/ST628XB UART AN1050 ST6 INPUT CAPTURE WITH ST62 16-BIT AUTO-RELOAD TIMER AN1127 USING THE ST62T6XC/5XC SPI IN MASTER MODE GENERAL AN683 MCUS - 8/16-BIT MICROCONTROLLERS (MCUS) APPLICATION NOTES ABSTRACTS BY TOPICS AN886 SELECTING BETWEEN ROM AND OTP FOR A MICROCONTROLLER AN887 MAKING IT EASY WITH MICROCONTROLLERS AN898 EMC
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ST6200C/ST6201C/ST6203C 14 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Revision Main Changes Date Pinout: Pin 10, TEST function is changed to non-user info. See Figure 2. Modification of Caution in Section 3.1.6.1. Addition of power consumption information in Section 3.3. Addition of Note in Section 7.2.4. 3.1 Modification of text (READ-MODIFY-WRITE instructions) in Section 7.2.5. 15 Jan 2001 Modification of Section 8.
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ST6200C/ST6201C/ST6203C NOTES: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.
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