Datasheet

ST7LITE0xY0, ST7LITESxY0
100/124
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET
Pin
T
A
= -40°C to 105°C, unless otherwise specified
Notes:
1. Data based on characterization results, not tested in production.
2. The I
IO
current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 82 and the
sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
3. The R
ON
pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
V
ILmax
and V
DD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET
pin with a duration below t
h(RSTL)in
can be ignored.
Symbol Parameter Conditions Min Typ Max Unit
V
IL
Input low level voltage V
SS
- 0.3 0.3xV
DD
V
V
IH
Input high level voltage 0.7xV
DD
V
DD
+ 0.3
V
hys
Schmitt trigger voltage hysteresis
1)
2V
V
OL
Output low level voltage
2)
V
DD
=5V
I
IO
=+5mA T
A
≤85°C
T
A
≤105°C
0.5
1.0
1.2
V
I
IO
=+2mA T
A
≤85°C
T
A
≤105°C
0.2
0.4
0.5
R
ON
Pull-up equivalent resistor
3) 1)
V
DD
=5V 20 40 80 kΩ
t
w(RSTL)out
Generated reset pulse duration Internal reset sources 30 µs
t
h(RSTL)in
External reset pulse hold time
4)
20 µs
t
g(RSTL)in
Filtered glitch duration 200 ns
1