Datasheet

ST7LITE0xY0, ST7LITESxY0
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SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d)
Figure 14. Clock Management Block Diagram
CR4CR7 CR0CR1CR2CR3CR6 CR5
RCCR
Tunable
PLL 1MHz -> 8MHz
CLKIN
Option byte
PLL 1MHz -> 4MHz
f
OSC
8MHz
4MHz
1MHz
0 to 8 MHz
MCCSR
SMS
MCO
MCO
f
CPU
f
CPU
TO CPU AND
PERIPHERALS
(1ms timebase @ 8 MHz f
OSC
)
/32 DIVIDER
f
OSC
f
OSC
/32
f
OSC
Oscillator1% RC
f
LTIMER
1
0
Option byte
LITE TIMER COUNTER
8-BIT
/2 DIVIDER
7
0
(except LITE
TIMER)
1